IS61QDB42M36 Datasheet, PDF (24/28 Pages) Integrated Silicon Solution, Inc – 72 Mb (2M x 36 & 4M x 18) QUAD (Burst of 4) Synchronous SRAMs

7^Q2 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 4) Synchronous SRAMs
I³
Instruction Set
Code
000
001
010
011
100
101
110
111
Instruction
EXTEST
IDCODE
SAMPLE-Z
PRIVATE
SAMPLE
PRIVATE
PRIVATE
BYPASS
TDO Output
Boundary Scan Register
32-bit Identification Register
Boundary Scan Register
Do not use
Boundary Scan Register
Do not use
Do not use
Bypass Register
Notes
2,6
1, 2
5
4
5
5
3
1. Places Qs in high-Z in order to sample all input data, regardless of other SRAM inputs.
2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data.
3. BYPASS register is initiated to V_SS when BYPASS instruction is invoked. The BYPASS register also holds the last serially loaded
TDI when exiting the shift-DR state.
4. SAMPLE instruction does not place DQs in high-Z.
5. This instruction is reserved. Invoking this instruction will cause improper SRAM functionality.
6. This EXTEST is not IEEE 1149.1-compliant. By default, it places Q in high-Z. If the internal register on the scan chain is set high,
Q will be updated with information loaded via a previous SAMPLE instruction. The actual transfer occurs during the update IR
state after EXTEST is loaded. The value of the internal register can be changed during SAMPLE and EXTEST only.
List of IEEE 1149.1 Standard Violations
• 7.2.1.b, e
• 7.7.1.a-f
• 10.1.1.b, e
• 10.7.1.a-d
• 6.1.1.d
JTAG Block Diagram
TDI
TMS
TCK
24
Bypass Register (1 bit)
Identification Register (32 bits)
Instruction Register (3 bits)
Control Signals
TAP Controller
TDO
Integrated Silicon Solution, Inc.
Rev. 
11/10/09