IS61QDB42M36 Datasheet, PDF (4/28 Pages) Integrated Silicon Solution, Inc – 72 Mb (2M x 36 & 4M x 18) QUAD (Burst of 4) Synchronous SRAMs

72 Mb (2M x 36 & 4M x 18)
QQUAD (Burst of 4) Synchronous SRAMs
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Block Diagram
D (Data-In)
36 (o r 18)
Data
Reg
19 (o r 20)
Add
Address
Reg
19 (or 20 )
R
W
BW _x
4 (or 2)
Cont rol
Logic
72 (or 36 ) 72 (or 36)
Wr ite Driver
2M x 36
(4M x 18)
Mem ory
Array
72
(or 36)
72
(or 36)
K
K
Cloc k
C
Gen
C
Select OutputControl
144
(or 72)
36 ( or 18)
Q (D ata- Out)
CQ, CQ
(Ech o Cloc k Out)
SRAM Features
Read Operations
The SRAM operates continuously in a burst-of-four mode. Read cycles are started by registering R in active
low state at the rising edge of the K clock. R can be activated every other cycle because two full cycles are
required to complete the burst of four in DDR mode. A second set of clocks, C and C, are used to control the
timing to the outputs. A set of free-running echo clocks, CQ and CQ, are produced internally with timings
identical to the data-outs. The echo clocks can be used as data capture clocks by the receiver device.
When the C and C clocks are connected high, the K and K clocks assume the function of those clocks. In this
case, the data corresponding to the first address is clocked 1.5 cycles later by the rising edge of the K clock.
The data corresponding to the second burst is clocked 2 cycles later by the following rising edge of the K
clock. The third data-out is clocked by the subsequent rising edge of the K clock, and the fourth data-out is
clocked by the subsequent rising edge of the K clock.
A NOP operation (R is high) does not terminate the previous read.
Write Operations
Write operations can also be initiated at every other rising edge of the K clock whenever W is low. The write
address is provided simultaneously. Again, the write always occurs in bursts of four.
The write data is provided in a ‘late write’ mode; that is, the data-in corresponding to the first address of the
burst, is presented 1 cycle later or at the rising edge of the following K clock. The data-in corresponding to the
second write burst address follows next, registered by the rising edge of K. The third data-in is clocked by the
subsequent rising edge of the K clock, and the fourth data-in is clocked by the subsequent rising edge of the
K clock.
4
Integrated Silicon Solution, Inc.
Rev. 
11/10/09