IS61QDB42M36 Datasheet, PDF (11/28 Pages) Integrated Silicon Solution, Inc – 72 Mb (2M x 36 & 4M x 18) QUAD (Burst of 4) Synchronous SRAMs

3^{72 Mb (2M x 36 & 4M x 18)}
Q^{QUAD (Burst of 4) Synchronous SRAMs}
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X18 Write Truth Table Use the following table with the Timing Reference Diagram for Truth Table on
page 9.
Operation
K(t+1) K(t+1.5) K(t+2) K(t+2.5) BW₀ BW₁
D_B
D_B+1
D_B+2
D_B+3
Write Byte 0 L→H
LH
D0-8 (t+1)
Write Byte 1 L→H
HL
D9-17 (t+1)
Write All Bytes L→H
L
L
D0-17 (t+1)
Abort Write L→H
HH
Don’t care
Write Byte 0
L→H
LH
D0-8 (t+1.5)
Write Byte 1
L→H
HL
D9-17 (t+1.5)
Write All Bytes
L→H
L
L
D0-17 (t+1.5)
Abort Write
L→H
HH
Don’t care
Write Byte 0
L→H
LH
D0-8 (t+2)
Write Byte 1
L→H
HL
D9-17 (t+2)
Write All Bytes
L→H
L
L
D0-17 (t+2)
Abort Write
L→H
HH
Don’t care
Write Byte 0
L→H L H
D0-8 (t+2.5)
Write Byte 1
L→H H L
D9-17 (t+2.5)
Write All Bytes
L→H L
L
D0-17 (t+2.5)
Abort Write
L→H H H
Don’t care
Notes;
1. For all cases. W needs to be active low during the rising edge of K occurring at time t.
2. For timing definitions refer to the AC Characteristics on page 17. Signals must have AC specifications with respect to switching
clocks K and K.
Integrated Silicon Solution, Inc.
11
Rev. 
11/10/09