IS61QDB42M36 Datasheet, PDF (10/28 Pages) Integrated Silicon Solution, Inc – 72 Mb (2M x 36 & 4M x 18) QUAD (Burst of 4) Synchronous SRAMs

7Q_Q2UMADb
(2M x 36 & 4M x 18)
(Burst of 4) Synchronous
SRAMs
I³
X36 Write Truth Table Use the following table with the Timing Reference Diagram for Truth Table on
page 9.
Operation
K(t+1) K(t+1.5) K(t+2) K(t+2.5) BW₀ BW₁ BW₂ BW₃
D_B
D_B+1
D_B+2
D_B+3
Write Byte 0 L→H
L
H
H
H D0-8 (t+1)
Write Byte 1 L→H
H
L
H
H D9-17 (t+1)
Write Byte 2 L→H
H
H
L
H D18-26 (t+1)
Write Byte 3 L→H
H H H L D27-35 (t+1)
Write All Bytes L→H
L
L
L
L D0-35 (t+1)
Abort Write L→H
H H H H Don’t care
Write Byte 0
L→H
L H HH
D0-8 (t+1.5)
Write Byte 1
L→H
H L HH
D9-17 (t+1.5)
Write Byte 2
L→H
HH LH
D18-26
(t+1.5)
Write Byte 3
L→H
HHHL
D27-35
(t+1.5)
Write All Bytes
L→H
L
L
L
L
D0-35 (t+1.5)
Abort Write
L→H
H H HH
Don’t care
Write Byte 0
L→H
L H HH
D0-8 (t+2)
Write Byte 1
L→H
H L HH
D9-17 (t+2)
Write Byte 2
L→H
HH LH
D18-26
(t+2)
Write Byte 3
L→H
HHHL
D27-35
(t+2)
Write All Bytes
L→H
L
L
L
L
D0-35 (t+2)
Abort Write
L→H
H H HH
Don’t care
Write Byte 0
L→H L H H H
D0-8 (t+2.5)
Write Byte 1
L→H H
L
HH
D9-17 (t+2.5)
Write Byte 2
L→H H H L H
D18-26 (t+2.5)
Write Byte 3
L→H H H H L
D27-35 (t+2.5)
Write All Bytes
L→H L
L
L
L
D0-35 (t+2.5)
Abort Write
L→H H H H H
Don’t care
Notes;
1. For all cases, W needs to be active low during the rising edge of K occurring at time t.
2. For timing definitions refer to the AC Characteristics on page 17. Signals must have AC specifications with respect to switching
clocks K and K.
10
Integrated Silicon Solution, Inc.
Rev. 
11/10/09