IS61QDB42M36 Datasheet, PDF (15/28 Pages) Integrated Silicon Solution, Inc – 72 Mb (2M x 36 & 4M x 18) QUAD (Burst of 4) Synchronous SRAMs

Q^{72 Mb (2M x 36 & 4M x 18)}
QUAD (Burst of 4) Synchronous SRAMs
I³
Typical AC Input Characteristics
Item
AC input logic high
AC input logic low
Clock input logic high (K, K, C, C)
Clock input logic low (K, K, C, C)
Symbol
V_IH (ac)
V_IL (ac)
V_IH-CLK (ac)
V_IL-CLK (ac)
Minimum
V_REF + 0.2
V_REF + 0.2
Maximum
V_REF - 0.2
V_REF - 0.2
Notes
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3
1, 2, 3
1. The peak-to-peak AC component superimposed on V_REF may not exceed 5% of the DC component of V_REF.
2. Performance is a function of V_IH and V_IL levels to clock inputs.
3. See the AC Input Definition diagram.
4. See the AC Input Definition diagram. The signals should swing monotonically with no steps rail-to-rail with input signals never ring-
ing back past VIH (AC) and VIL (AC) during the input setup and input hold window. VIH (AC) and VIL (AC) are used for timing pur-
poses only.
AC Input Definition
K
V_REF
K
V_RAIL
V_IH (AC)
V_REF
V_IL (AC)
V_-RAIL
Setup
Time
Hold
Time
Programmable Impedance Output Driver DC Electrical Characteristics
(T_A = 0 to +70° C, V_DD = 1.8V -5%, +5%, V_DDQ = 1.5, 1.8V)
Parameter
Symbol
Minimum
Maximum
Units
Output “high” level voltage
V_OH
V_DDQ / 2
V_DDQ
V
Output “low” level voltage
V_OL
V_SS
1.
I_OH
=


V-----D---2--D-----Q---_
⁄
^R---5--Q--- ^{± 15% @ V}OH ^{= V}DDQ ^{/ 2 For: 175Ω ≤RQ ≤350Ω.}
V_DDQ / 2
V
2.
I_OL
=


V-----D---2--D-----Q---_
⁄


R---5--Q---_
± 15%
@
V_OL
=
V_DDQ
/
2
For:
175Ω
≤RQ
≤350Ω.
3. Parameter tested with RQ = 250Ω and V_DDQ = 1.5V.
Notes
1, 3
2, 3
Integrated Silicon Solution, Inc.
15
Rev. 
11/10/09