IS61QDB42M36 Datasheet, PDF (17/28 Pages) Integrated Silicon Solution, Inc – 72 Mb (2M x 36 & 4M x 18) QUAD (Burst of 4) Synchronous SRAMs

72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 4) Synchronous SRAMs
AC CHARACTERISTICS(VDD=1.8V 0.1V, TA=0 C to +70 C)
PARAMETER
33 (300 MHz)
SYMBOL
MIN MAX
Clock
Clock Cycle Time (K, K, C, C)
tKHKH 3.30 7.5
Clock Phase Jitter (K, K, C, C)
tKC var
0.20
Clock High Time (K, K, C, C)
tKHKL
1.32
Clock Low Time (K, K, C, C)
tKLKH
1.32
Clock to Clock (K K , C C )
tKHKH
1.49
Clock to data clock (K C , K C )
tKHCH
0.00 0.8
DLL Lock Time (K, C)
tKC lock 1024
Doff Low period to DLL reset
tDo LowToReset 5
Output Times
C, C High to Output Valid
tCHQV
0.45
C, C High to Output Hold
tCHQX -0.45
C, C High to Echo Clock Valid
tCHCQV
0.40
C, C High to Echo Clock Hold
tCHCQX -0.40
CQ, CQ High to Output Valid
tCQHQV
0.27
CQ, CQ High to Output Hold
tCQHQX -0.27
C, High to Output High-Z
tCHQZ
0.45
C, High to Output Low-Z
tCHQX1 -0.45
Setup Times
Address valid to K rising edge
tAVKH
0.35
Control inputs valid to K rising edge tIVKH 0.35
Data-in valid to K, K rising edge
tDVKH
0.35
Hold Times
K rising edge to address hold
tKHAX
0.35
K rising edge to control inputs hold tKHIX 0.35
K, K rising edge to data-in hold
tKHDX
0.35
40 (250 MHz)
MIN MAX
4.00 7.5
0.20
1.60
1.60
1.80
0.00 0.8
1024
5
0.45
-0.45
0.40
-0.40
0.30
-0.30
0.45
-0.45
0.35
0.35
0.35
0.35
0.35
0.35
50 (200 MHz)
MIN MAX
5.00 7.5
0.20
2.00
2.00
2.20
0.00 0.8
1024
5
0.45
-0.45
0.40
-0.40
0.35
-0.35
0.45
-0.45
0.4
0.4
0.4
0.4
0.4
0.4
UNIT NOTE
ns
ns
5
ns
ns
ns
ns
cycle 6
ns
ns
3
ns
3
ns
ns
ns
7
ns
7
ns
3
ns
3
ns
ns
2
ns
ns
ns
ns
Notes: 1. All address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control singles are R, W,BW0,BW1 and (BW2, BW3, also for x36)
3. If C,C are tied high, K,K become the references for C,C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ.
The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worst case at totally different test conditions
(0 C, 1.9V) than tCHQZ, which is a MAX parameter (worst case at 70 C, 1.7V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
6. Vdd slew rate must be less than 0.1V DC per 50ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.
7. Echo clock is very tightly controlled to data valid/data hold. By design, there is a + 0.1ns variation from echo clock to data.
The data sheet parameters reflect tester guard bands and test setup variations.
Integrated Silicon Solution, Inc.
17
Rev. B
11/10/09