IS61QDB42M36 Datasheet, PDF (5/28 Pages) Integrated Silicon Solution, Inc – 72 Mb (2M x 36 & 4M x 18) QUAD (Burst of 4) Synchronous SRAMs

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(2M x 36 & 4M x 18)
(Burst of 4) Synchronous
SRAMs
I³
The data-in provided for writing is initially kept in write buffers. The information in these buffers is written into
the array on the third write cycle. A read cycle to the last two write addresses produces data from the write
buffers. The SRAM maintains data coherency.
During a write, the byte writes independently control which byte of any of the four burst addresses is written
(see X18/X36 Write Truth Tables on page 10 and Timing Reference Diagram for Truth Table on page 8).
Whenever a write is disabled (W is high at the rising edge of K), data is not written into the memory.
RQ Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V_SS to enable the SRAM
to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance
driven by the SRAM. For example, an RQ of 250Ω results in a driver impedance of 50Ω. The allowable range
of RQ to guarantee impedance matching is between 175Ω and 350Ω, with the tolerance described in
Programmable Impedance Output Driver DC Electrical Characteristics on page 16. The RQ resistor should
be placed less than two inches away from the ZQ ball on the SRAM module. The capacitance of the loaded
ZQ trace must be less than 3 pF.
The ZQ pin can also be directly connected to V_DDQ to obtain a minimum impedance setting. ZQ must never
be connected to V_SS.
Programmable Impedance and Power-Up Requirements
Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by
drifts in supply voltage and temperature. At power-up, the driver impedance is in the middle of allowable
impedances values. The final impedance value is achieved within 1024 clock cycles.
Single Clock Mode
This device can be also operated in single-clock mode. In this case, C and C are both connected high at
power-up and must never change. Under this condition, K and K will control the output timings.
Either clock pair must have both polarities switching and must never connect to V_REF, as they are not differ-
ential clocks
Depth Expansion
Separate input and output ports enable easy depth expansion, as each port can be selected and deselected
independently. Read and write operations can occur simultaneously without affecting each other. Also, all
pending read and write transactions are always completed prior to deselecting the corresponding port.
In the following application example, the second pair of C and C clocks is delayed such that the return data
meets the data setup and hold times at the memory controller.
Integrated Silicon Solution, Inc.
5
Rev. 
11/10/09