X40231 Datasheet, PDF (8/36 Pages) Intersil Corporation – Triple Voltage Monitors, POR, 2 kbit EEPROM MEMORY, and Single/Dual DCP

X40231, X40233, X40235, X40237, X40239
SCL
SDA
Data Stable
Data Change
Data Stable
Figure 1. Valid Data Changes on the SDA Bus
DETAILED DEVICE DESCRIPTION
The X4023x combines One or Two Intersil Digitally
Controlled Potentiometer (XDCP) devices, V_CC
power-on reset control, V_CC low voltage reset control,
two supplementary voltage monitors with independent
outputs, and integrated EEPROM with Block Lock™
protection, in one package. The integrated functional-
ity of the X4023x lowers system cost, increases reli-
ability, and reduces board space requirements.
DCPs allow for the “set-and-forget” adjustment during
production test or in-system updating via the industry
standard 2-wire interface.
Applying voltage to V_CC activates the Power-on Reset
circuit which sets the RESET output HIGH, until the
supply voltage stabilizes for a period of time (50-300
msec selectable via software). The RESET output then
goes LOW. The Low Voltage Reset circuit sets the
RESET output HIGH when V_CC falls below the mini-
mum V_CC trip point. RESET remains HIGH until V_CC
returns to proper operating level and stabilizes for a
period of time (t_PURST). A Manual Reset (MR) input
allows the user to externally activate the RESET output.
Two supplementary Voltage Monitor circuits, V2MON
and V3MON, continuously compare their inputs to
individual trip voltages (independent on-chip voltage
references factory set and user programmable). When
an input voltage exceeds it’s associated trip level, the
corresponding output (V3FAIL, V2FAIL) goes HIGH.
When the input voltage becomes lower than it’s asso-
ciated trip level, the corresponding output is driven
LOW. A corresponding binary representation of the
two monitor circuit outputs (V2FAIL and V3FAIL) are
also stored in latched, volatile (CR) register bits. The
status of these two monitor outputs can be read out via
the 2-wire serial port. The bits will remain SET, even
after the alarm condition is removed, allowing
advanced recovery algorithms to be implemented.
Intersil’s unique circuits allow for all internal trip voltages
to be individually programmed with high accuracy,
either by Intersil at final test or by the user during their
production process. Some distributors offer V_TRIP
reprogramming as a value added service. This gives
the designer great flexibility in changing system param-
eters, either at the time of manufacture, or in the field.
The memory portion of the device is a CMOS serial
EEPROM array with Intersil’s Block Lock^TM protection.
This memory may be used to store module manufactur-
ing data, serial numbers, or various other system
parameters. The EEPROM array is internally organized
as x 8, and utilizes Intersil’s proprietary Direct Write^TM
cells providing a minimum endurance of 1,000,000
cycles and a minimum data retention of 100 years.
The device features a 2-Wire interface.
PRINCIPLES OF OPERATION
SERIAL INTERFACE
Serial Interface Conventions
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. The X4023x operates as a slave in
all applications.
Serial Clock and Data
Data states on the SDA line can change only while
SCL is LOW (see Figure 1). SDA state changes while
SCL is HIGH are reserved for indicating START and
STOP conditions. See Figure 1. On power-up of the
X4023x, the SDA pin is in the input mode.
8
FN8115.0
April 11, 2005