X40231 Datasheet, PDF (4/36 Pages) Intersil Corporation – Triple Voltage Monitors, POR, 2 kbit EEPROM MEMORY, and Single/Dual DCP

X40231, X40233, X40235, X40237, X40239
X40233 PIN ASSIGNMENT
SOIC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
NC
NC
V3MON
V3FAIL
MR
WP
SCL
SDA
VSS
R_W1
R_H1
NC
V2MON
V2FAIL
RESET
V_CC
Function
No Connect
No Connect
V3MON Voltage Monitor Input.
V3MON is the input to a non-inverting voltage comparator circuit. When the V3MON input is higher than
the V_TRIP3 threshold voltage, V3FAIL makes a transition to a HIGH level. Connect V3MON to V_SS when
not used.
V3MON RESET Output.
This open drain output makes a transition to a HIGH level when V3MON is greater than V_TRIP3 and goes
LOW when V3MON is less than VTRIP3. There is no delay circuitry on this pin. The V3FAIL pin requires
the use of an external “pull-up” resistor.
Manual Reset.
MR is a TTL level compatible input. Pulling the MR pin active (HIGH) initiates a reset cycle to the RESET
pin (V_CC RESET Output pin). RESET will remain HIGH for time t_PURST after MR has returned to it’s
normally LOW state. The reset time can be selected using bits PUP1 and PUP0 in the CR Register. The
MR pin requires the use of an external “pull-down” resistor.
Write Protect Control Pin.
WP pin is a TTL level compatible input. When held HIGH, Write Protection is enabled. In the enabled
state, this pin prevents all nonvolatile “write” operations. Also, when the Write Protection is enabled, and
the device Block Lock feature is active (i.e. the Block Lock bits are NOT [0,0]), then no “write” (volatile
or nonvolatile) operations can be performed in the device (including the wiper position of any of the
integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an internal “pull-down” resistor,
thus if left floating the write protection feature is disabled.
Serial Clock.
This is a TTL level compatible input pin used to control the serial bus timing for data input and output.
Serial Data.
SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the device. The SDA
pin input buffer is always active (not gated). This pin requires an external pull up resistor.
Ground.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP.
Connection to end of resistor array for (the 100 Tap) DCP.
No Connect
V2MON Voltage Monitor Input.
V2MON is the input to a non-inverting voltage comparator circuit. When the V2MON input is greater than
the V_TRIP2 threshold voltage, V2FAIL makes a transition to a HIGH level. Connect V2MON to V_SS when
not used.
V2MON RESET Output.
This open drain output makes a transition to a HIGH level when V2MON is greater than V_TRIP2, and goes
LOW when V2MON is less than V_TRIP2. There is no power-up reset delay circuitry on this pin. The
V2FAIL pin requires the use of an external “pull-up” resistor.
V_CC RESET Output.
This is an active HIGH, open drain output which becomes active whenever V_CC falls below V_TRIP1.
RESET becomes active on power-up and remains active for a time t_PURST after the power supply
stabilizes (t_PURST can be changed by varying the PUP0 and PUP1 bits of the internal control register).
The RESET pin requires the use of an external “pull-up” resistor. The RESET pin can be forced active
(HIGH) using the manual reset (MR) input pin.
Supply Voltage.
4
FN8115.0
April 11, 2005