X40231 Datasheet, PDF (15/36 Pages) Intersil Corporation – Triple Voltage Monitors, POR, 2 kbit EEPROM MEMORY, and Single/Dual DCP

X40231, X40233, X40235, X40237, X40239
S
Signals from t
the Master
a
r
t
Slave
Address
Address
Byte
(2 < n < 16)
S
t
Data
Data
o
(1)
(n)
p
SDA Bus
Signals from
the Slave
1 01 00 00 0
A
C
K
A
C
K
A
C
K
A
C
K
Figure 12. EEPROM Page Write Operation
EEPROM Byte Write
In order to perform an EEPROM Byte Write operation
to the EEPROM array, the Write Enable Latch (WEL)
bit of the CR Register must first be set (See “BL1, BL0:
Block Lock protection bits - (Nonvolatile)” on page 18.)
For a write operation, the X4023x requires the Slave
Address Byte and an Address Byte. This gives the
master access to any one of the words in the array.
After receipt of the Address Byte, the X4023x
responds with an ACKNOWLEDGE, and awaits the
next eight bits of data. After receiving the 8 bits of the
Data Byte, it again responds with an ACKNOWL-
EDGE. The master then terminates the transfer by
generating a STOP condition, at which time the
X4023x begins the internal write cycle to the nonvola-
tile memory (See Figure 11). During this internal write
cycle, the X4023x inputs are disabled, so it does not
respond to any requests from the master. The SDA
output is at high impedance. A write to a region of
EEPROM memory which has been protected with the
Block-Lock feature (See “BL1, BL0: Block Lock protec-
tion bits - (Nonvolatile)” on page 18.), suppresses the
ACKNOWLEDGE bit after the Address Byte.
EEPROM Page Write
In order to perform an EEPROM Page Write operation
to the EEPROM array, the Write Enable Latch (WEL)
bit of the CR Register must first be set (See “BL1, BL0:
Block Lock protection bits - (Nonvolatile)” on page 18.)
The X4023x is capable of a page write operation. It is
initiated in the same manner as the byte write opera-
tion; but instead of terminating the write cycle after the
first data byte is transferred, the master can transmit
an unlimited number of 8-bit bytes. After the receipt of
each byte, the X4023x responds with an ACKNOWL-
EDGE, and the address is internally incremented by
one. The page address remains constant. When the
counter reaches the end of the page, it “rolls over” and
goes back to ‘0’ on the same page.
For example, if the master writes 12 bytes to the page
starting at location 11 (decimal), the first 5 bytes are
written to locations 11 through 15, while the last 7
bytes are written to locations 0 through 6. Afterwards,
the address counter would point to location 7. If the
master supplies more than 16 bytes of data, then new
data overwrites the previous data, one byte at a time
(See Figure 13).
The master terminates the Data Byte loading by issu-
ing a STOP condition, which causes the X4023x to
begin the nonvolatile write cycle. As with the byte write
operation, all inputs are disabled until completion of
the internal write cycle. See Figure 12 for the address,
ACKNOWLEDGE, and data transfer sequence.
Stops and EEPROM Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte and receiving the subsequent ACKNOWLEDGE
signal. If the master issues a STOP within a Data Byte,
or before the X4023x issues a corresponding
ACKNOWLEDGE, the X4023x cancels the write oper-
ation. Therefore, the contents of the EEPROM array
does not change.
EEPROM Array Read Operations
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current EEPROM Address
Read, Random EEPROM Read, and Sequential
EEPROM Read.
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FN8115.0
April 11, 2005