X40231 Datasheet, PDF (18/36 Pages) Intersil Corporation – Triple Voltage Monitors, POR, 2 kbit EEPROM MEMORY, and Single/Dual DCP

X40231, X40233, X40235, X40237, X40239
CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0
PUP1 V2FS V3FS BL1 BL0 RWEL WEL _PUP0
NV
NV NV
NV
Bit(s)
Description
WEL
Write Enable Latch bit
RWEL
Register Write Enable Latch bit
V2FS
V2MON Output Flag Status
V3FS
V3MON Output Flag Status
BL1 - BL0
Sets the Block Lock partition
PUP1 - PUP0 Sets the Power-on Reset time
NOTE: Bits labelled NV are nonvolatile (See “CONTROL AND STATUS REGISTER”).
Figure 17. CR Register Format
CONTROL AND STATUS REGISTER
The Control and Status (CR) Register provides the user
with a mechanism for changing and reading the status
of various parameters of the X4023x (See Figure 17).
The CR register is a combination of both volatile and
nonvolatile bits. The nonvolatile bits of the CR register
retain their stored values even when V_CC is powered
down, then powered back up. The volatile bits how-
ever, will always power-up to a known logic state “0”
(irrespective of their value at power-down).
A detailed description of the function of each of the CR
register bits follows:
WEL: Write Enable Latch (Volatile)
The WEL bit controls the Write Enable status of the
entire X4023x device. This bit must first be enabled
before ANY write operation (to DCPs, EEPROM mem-
ory array, or the CR register). If the WEL bit is not first
enabled, then ANY proceeding (volatile or nonvolatile)
write operation to DCPs, EEPROM array, as well as
the CR register, is aborted and no ACKNOWLEDGE is
issued after a Data Byte.
The WEL bit is a volatile latch that powers up in the
disabled, LOW (0) state. The WEL bit is enabled / set
by writing 00000010 to the CR register. Once enabled,
the WEL bit remains set to “1” until either it is reset to
“0” (by writing 00000000 to the CR register) or until the
X4023x powers down, and then up again.
Writes to the WEL bit do not cause an internal high
voltage write cycle. Therefore, the device is ready for
another operation immediately after a STOP condition
is executed in the CR Write command sequence (See
Figure 18).
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit controls the (CR) Register Write Enable
status of the X4023x. Therefore, in order to write to
any of the bits of the CR Register (except WEL), the
RWEL bit must first be set to “1”. The RWEL bit is a
volatile bit that powers up in the disabled, LOW (“0”)
state.
It must be noted that the RWEL bit can only be set,
once the WEL bit has first been enabled (See "CR
Register Write Operation").
The RWEL bit will reset itself to the default “0” state, in
one of three cases:
—After a successful write operation to any bits of the CR
register has been completed (See Figure 18).
—When the X4023x is powered down.
—When attempting to write to a Block Lock protected
region of the EEPROM memory (See "BL1, BL0: Block
Lock protection bits - (Nonvolatile)", below).
BL1, BL0: Block Lock protection bits - (Nonvolatile)
The Block Lock protection bits (BL1 and BL0) are used
to:
—Inhibit a write operation from being performed to cer-
tain addresses of the EEPROM memory array
—Inhibit a DCP write operation (changing the “wiper
position”).
The region of EEPROM memory which is protected /
locked is determined by the combination of the BL1
and BL0 bits written to the CR register. It is possible to
lock the regions of EEPROM memory shown in the
table below:
BL1 BL0
00
01
10
11
Protected Addresses
(Size)
None (Default)
C0_h - FF_h (64 bytes)
80_h - FF_h (128 bytes)
00_h - FF_h (256 bytes)
Partition of array
locked
None (Default)
Upper 1/4
Upper 1/2
All
If the user attempts to perform a write operation on a
protected region of EEPROM memory, the operation
is aborted without changing any data in the array.
18
FN8115.0
April 11, 2005