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X40231 Datasheet, PDF (30/36 Pages) Intersil Corporation – Triple Voltage Monitors, POR, 2 kbit EEPROM MEMORY, and Single/Dual DCP
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X40231, X40233, X40235, X40237, X40239
A.C. CHARACTERISTICS (See Figure 27, Figure 28, Figure 29)
Symbol
fSCL
tIN(5)
tAA
tBUF
tLOW
tHIGH
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tDH
tR(5)
tF(5)
tSU:WP
tHD:WP
Cb
Parameter
SCL Clock Frequency
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus free before start of new transmission
Clock LOW Time
Clock HIGH Time
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
Data In Hold Time
Stop Condition Setup Time
Data Output Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
WP Setup Time
WP Hold Time
Capacitive load for each bus line
400kHz
Min
Max
0
400
50
0.1
0.9
1.3
1.3
0.6
0.6
0.6
100
0
0.6
50
20 +.1Cb(2)
300
20 +.1Cb(2)
300
0.6
0
400
Units
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
µs
ns
ns
ns
µs
µs
pF
A.C. TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
0.1VCC to 0.9VCC
10ns
0.5VCC
See Figure 25
NONVOLATILE WRITE CYCLE TIMING
Symbol
tWC(4)
Parameter
Nonvolatile Write Cycle Time
Min.
Typ.(1)
5
Max.
10
Units
ms
CAPACITANCE (TA = 25°C, F = 1.0 MHZ, VCC = 5V)
Symbol
Parameter
Max
COUT(5)
Output Capacitance (SDA, RESET, V2FAIL, V3FAIL)
8
CIN(5)
Input Capacitance (SCL, WP, MR)
6
Units
pF
pF
Test Conditions
VOUT = 0V
VIN = 0V
Notes: 1. Typical values are for TA = 25°C and VCC = 5.0V
Notes: 2. Cb = total capacitance of one bus line in pF.
Notes: 3. Over recommended operating conditions, unless otherwise specified
Notes: 4. tWC is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Notes: 5. This parameter is not 100% tested.
30
FN8115.0
April 11, 2005
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