X40231 Datasheet, PDF (16/36 Pages) Intersil Corporation – Triple Voltage Monitors, POR, 2 kbit EEPROM MEMORY, and Single/Dual DCP

X40231, X40233, X40235, X40237, X40239
7 bytes
5 b5ybteytess
address
= 6₁₀
address
11₁₀
address
15 ₁₀
address pointer
ends here
Addr = 7₁₀
Figure 13. Example: Writing 12 bytes to a 16-byte page starting at location 11.
Signals from
S
the Master
t
Slave
S
a
r
Address
t
o
t
p
SDA Bus
1 0100001
Signals from
the Slave
A
C
K
Data
Figure 14. Current EEPROM Address Read Sequence
Current EEPROM Address Read
Internally the device contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power-up, the address of the
address counter is undefined, requiring a read or write
operation for initialization.
Upon receipt of the Slave Address Byte with the R/W
bit set to one, the device issues an ACKNOWLEDGE
and then transmits the eight bits of the Data Byte. The
master terminates the read operation when it does not
respond with an ACKNOWLEDGE during the ninth
clock and then issues a STOP condition (See Figure
14 for the address, ACKNOWLEDGE, and data trans-
fer sequence).
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a STOP condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a STOP condition.
Another important point to note regarding the “Current
EEPROM Address Read” , is that this operation is not
available if the last executed operation was an access
to a DCP or the CR Register (i.e.: an operation using
the Device Type Identifier 1010111 or 1010010).
Immediately after an operation to a DCP or CR Regis-
ter is performed, only a “Random EEPROM Read” is
available. Immediately following a “Random EEPROM
Read” , a “Current EEPROM Address Read” or
“Sequential EEPROM Read” is once again available
(assuming that no access to a DCP or CR Register
occur in the interim).
Random EEPROM Read
Random read operation allows the master to access
any memory location in the array. Prior to issuing the
Slave Address Byte with the R/W bit set to one, the
master must first perform a “dummy” write operation.
The master issues the START condition and the Slave
Address Byte, receives an ACKNOWLEDGE, then
issues an Address Byte. This “dummy” Write operation
sets the address pointer to the address from which to
begin the random EEPROM read operation.
After the X4023x acknowledges the receipt of the
Address Byte, the master immediately issues another
START condition and the Slave Address Byte with the
R/W bit set to one. This is followed by an ACKNOWL-
EDGE from the X4023x and then by the eight bit word.
16
FN8115.0
April 11, 2005