X40231 Datasheet, PDF (1/36 Pages) Intersil Corporation – Triple Voltage Monitors, POR, 2 kbit EEPROM MEMORY, and Single/Dual DCP

X40231, X40233, X40235, X40237, X40239
®
Integrated System Management IC
Data Sheet
April 11, 2005
FN8115.0
Triple Voltage Monitors, POR, 2 kbit
EEPROM Memory, and Single/Dual DCP
FEATURES
• Triple Voltage Monitors
—User Programmable Threshold Voltage
—Power-on Reset (POR) Circuitry
—Software Selectable Reset timeout
—Manual Reset Input
• 2-Wire industry standard Serial Interface
• 2 kbit EEPROM with Write Protect & Block Lock^TM
• Digitally Controlled Potentiometers (DCP)
X4023X Family Selector Guide
X= 256 tap 100 tap 64 Tap
1
1
3
1
51
71
1
91
1
—Total Resistance
256 Tap = 100kΩ, 100 Tap or 64 Tap = 10kΩ
—Nonvolatile wiper position
—Write Protect Function
• Single Supply Operation
—2.7V to 5.5V
• 16 Pin SOIC (300) package
— SOIC
DESCRIPTION
The X4023x family of Integrated System Manage-
ment ICs combine CPU Supervisor functions (V_CC
Power-onpower-on Reset (POR) circuitry, two addi-
tional programmable voltage monitor inputs with soft-
ware and hardware indicators), integrated EEPROM
with Block Lock^TM protection and one or two Intersil
Digitally Controlled Potentiometers (XDCP). All func-
tions of the X4023x are accessed by an industry
standard 2-Wire serial interface.
APPLICATIONS
The DCP of the X4023x may be utilized to software
control analog voltages for:
– LCD contrast, LCD purity, or Backlight control.
– Power Supply settings such as PWM frequency,
Voltage Trimming or Margining (temperature offset
control).
– Reference voltage setting (e.g. DDR-SDRAM SSTL-2)
The 2 kbit integrated EEPROM may be used to store
ID, manufacturer data, maintenance data and module
definition data.
The programmable POR circuit insures V_CC is stable
before RESET is removed and protects against
brown-outs and power failures. The programmable
voltage monitors have on-chip independent reference
alarm levels. With separate outputs, the voltage moni-
tors can be used for power-on sequencing.
BLOCK DIAGRAM
8
R_H
WP
PROTECT LOGIC
WIPER
COUNTER
R_W
256 Tap DCP
REGISTER
DATA
REGISTER
4
SDA
COMMAND
DECODE &
SCL
CONTROL
LOGIC
THRESHOLD
RESET LOGIC
Manual Reset (MR)
V3MON
-
VTRIP₃ ⁺
V2MON
-
VTRIP₂ ⁺
V_CC
+
V_SS
VTRIP₁ –
©2000 Intersil Inc., Patents Pending (VTRIP_1,2,3 are user programmable)
CR
REGISTER
2 kbit
EEPROM
ARRAY
2
8 - BIT
NONVOLATILE
MEMORY
WIPER
COUNTER
REGISTER
8 - BIT
NONVOLATILE
MEMORY
POWER-ON /
LOW VOLTAGE
RESET
GENERATION
R_H
R_W
Optional
64 or 100 Tap DCP
V3FAIL
V2FAIL
RESET
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.