X40231 Datasheet, PDF (21/36 Pages) Intersil Corporation – Triple Voltage Monitors, POR, 2 kbit EEPROM MEMORY, and Single/Dual DCP

X40231, X40233, X40235, X40237, X40239
MR: Manual Reset
The RESET output can be forced HIGH externally using
the Manual Reset (MR) input. MR is a de-bounced, TTL
compatible input, and so it may be operated by con-
necting a push-button directly from V_CC to the MR pin.
RESET remains HIGH for time t_PURST after MR has
returned to its LOW state (See Figure 19). An exter-
nal “pull down” resistor is required to hold this pin
(normally) LOW.
V_CC
0 Volts
MR
0 Volts
V_TRIP1
RESET
0 Volts
t_PURST
Figure 19. Manual Reset Response
Signals from the
Master
SDA Bus
Signals from the
Slave
WRITE Operation
READ Operation
S
t
a
r
Slave
Address
t
S
Address Byte
t
Slave
a
r
Address
t
S
t
o
p
CS7 … CS0
1010010 0
1010010 1
A
A
C
C
K
K
A
C
K
Data
“Dummy” Write
Figure 20. CR Register Read Command Sequence
X4023x Write Permission Status
Block Lock
Bits
DCP Volatile Write
BL0 BL1 WP
Permitted
x
1
1
NO
1
x
1
NO
0
0
1
YES
x
1
0
NO
1
x
0
NO
0
0
0
YES
DCP Nonvolatile
Write Permitted
NO
NO
NO
NO
NO
YES
Write to EEPROM
Permitted
NO
NO
NO
Not in locked region
Not in locked region
Yes (All Array)
Write to CR Register
Permitted
Volatile Bits Nonvolatile Bits
YES
NO
YES
NO
YES
NO
YES
YES
YES
YES
YES
YES
21
FN8115.0
April 11, 2005