ISL78227 Datasheet, PDF (7/43 Pages) Intersil Corporation – 2-Phase Boost Controller with Integrated Drivers

Block Diagram
VIN
HIC/LATCH
PGOOD
EN
PVCC
VCC
SS
ATRK/DTRK
TRACK
FB
COMP
IMON
1.21V
EN
÷ 48 ^VIN/48
1.21V
5.2V
LDO
POR
PLL
OTP
VIN_OV
1.2*VREF_1.6V
VFB
HICCUP
0.8*VREF_1.6V
EN
/LATCHOFF
EN_HICCP
EN_LATCHOFF
INITIALIZATION
DELAY
HICCUP
RETRY
DELAY
LATCH-OFF
LOGIC
5µA
EN_SS
SOFT-START
DELAYAND
LOGIC
3.47V
SS
SS_DONE
VOUT_OV
VOUT_UV
VIN_OV
VOUT_OV
OC_AVG
EN
OC2_PEAK_PH1
OC2_PEAK_PH2
PLLCOMP_SHORT
PLL_LOCK
DELAY
FAULT LOGIC
FAULT
CLOCK
VCO
PLL
SLOPE
COMPENSATION
112µA
ATRAK/
DTRK
1k
0.3V
VREF_TRK
VREF_2.5V
SS ₊
M
U
X
LP
Filter
VREF_TRK
VREF_1.6V
+ _Gm1
+
VFB _-
PWM
COMPARATOR
+
-
VRAMP
OC2_PEAK_PH1
OC1_PH1
OC_NEG_PH1
ZCD_PH1
ISEN1
ISEN1
105µA _ISEN1
80µA
ISEN1
-48µA _ISEN1
2µA
CSA
112µA
DCC
VREF_CC(1.6V) +
Gm2
-
1.1V
CMP_PD
+
PHASE_DROP
-
VIMON
CMP_OCAVG
2V +
OC_AVG
-
IOUT
FAULT
R2
R1 Q
CLOCK _S
PWM CONTROL
PROGRAMMABLE
ADAPTIVE DEAD
TIME
PVCC
DUPLICATE FOR EACH PHASE
PGND
DROP_PHASE2
÷8
ISEN1
(PHASE1)
PHASE DROP
CONTROL

17µA

÷8
ISEN2
(PHASE2)
SGND
(BOTTOM PAD)
EN_DE
EN_PHASE_DROP
DE MODE
AND PHASE DROP MODE
SELECTION
FIGURE 3. BLOCK DIAGRAM
FSYNC
PLLCOMP
CLKOUT
SLOPE
ISEN1P
ISEN1N
BOOT1
UG1
PH1
LG1
PGND
RDT
RBLANK
DE/PHDRP