ISL78227 Datasheet, PDF (33/43 Pages) Intersil Corporation – 2-Phase Boost Controller with Integrated Drivers

ISL78227
3. When DE/PHDRP = GND, both diode emulation and phase
drop functions are disabled. The part is set in Continuous
Conduction Mode (CCM).
TABLE 2. CCM/DE/PH_DROP MODE SETTING (DE/PHDRP PIN)
MODE NUMBER
(NAME)
DE/PHDRP PIN
SETTING
PHASE-DROP
DE MODE
MODE
1 (DE)
VCC
Enabled
Disabled
2 (DE+PH_DROP)
FLOAT
Enabled
Enabled
3 (CCM)
GND
Disabled
Disabled
AUTOMATIC PHASE DROPPING/ADDING
When the phase drop function is enabled, the ISL78227
automatically drops or adds Phase 2 by comparing the V_IMON to
the phase dropping/adding thresholds. V_IMON is proportional to
the average input current indicating the level of the load.
The phase dropping mode is not allowed with external
synchronization.
Phase Dropping
When load current drops and V_IMON falls below 1.1V, Phase 2 is
disabled. For better transient response during phase dropping,
the ISL78227 will gradually reduce the duty cycle of the phase
from steady state to zero, typically within 8 to 10 switching
cycles. This gradual dropping scheme will help smooth the
change of the PWM signal and stabilize the system when phase
dropping happens.
From Equations 13 and 14, the phase dropping current threshold
level for the total 2-phase boost input current can be calculated
by Equation 16.
I_INphDRP
=


-_R----_I-¹-_M--^.--¹-_O----_N--
–
17

10^–6_
 _R-^R----_SS----_EE----_NT--  8A
(EQ. 16)
Phase Adding
The phase adding is decided by two mechanisms listed below.
The Phase 2 will be added immediately if either of the two
following conditions are met.
1. V_IMON > 1.15V, the IMON pin voltage is higher than phase
adding threshold 1.15V. The phase adding current threshold
level for the total 2-phase boost input current can be
calculated by Equation 17.
I_INphADD
=


-_R---¹-_I--_M-^.-¹---_O-⁵---_N--
–
17

10^–6_
 _R-^R----_SS----_EE----_NT--  8A
(EQ. 17)
2. I_SENx > 80µA (OC1), individual phase current triggers OC1.
The first is similar to the phase dropping scheme. When the load
increases causing V_IMON>1.15V, Phase 2 will be added back
immediately to support the increased load demand. Since the
IMON pin normally has large RC filter and V_IMON is average
current signal, this mechanism has a slow response and is
intended for slow load transients.
The second mechanism is intended to handle the case when load
increases quickly. If the quick load increase triggers OC1
(I_SENx>80µA) in either of the 2 phases, Phase 2 will be added
back immediately.
After Phase 2 is added, the phase dropping function will be
disabled for 1.5ms. After this 1.5ms expires, the phase dropping
circuit will be activated again and Phase 2 can be dropped
automatically as usual.
DIODE EMULATION AT LIGHT LOAD CONDITION
When the Diode Emulation mode (DE) is selected to be enabled
(Mode 1 and 2 in Table 2), the ISL78227 has cycle-by-cycle diode
emulation operation at light load achieving Discontinuous
Conduction Mode (DCM) operation. With DE mode operation,
negative current is prevented and the conduction loss is reduced,
therefore high efficiency can be achieved at light load conditions.
Diode emulation occurs during t₅-t₈ (on Figure 58 on page 29),
regardless of the DE/PHDRP operating modes (Table 2).
PULSE SKIPPING AT DEEP LIGHT LOAD CONDITION
If the converter enters diode emulation mode and the load is still
reducing, eventually pulse skipping will occur to increase the
deep light-load efficiency. Either Phase 1 or Phase 2, or both, will
be pulse skipping at these deep light load conditions.
Fault Protections/Indications and Current
Limiting
The ISL78227 is implemented with comprehensive fault
protections/indications and current limitings to design a highly
reliable boost converter. Most of the fault protections’ response
can be selected to be either Hiccup or Latch-off by configuring
the HIC/LATCH pin, which offers the flexibility upon the specific
requirements for different applications.
Selectable Hiccup or Latch-Off Fault Response
Table 3 on page 34 lists the fault protections that can have either
Hiccup or Latch-off fault response determined by HIC/LATCH pin
configurations.
• When the HIC/LATCH pin is pulled high (VCC), the fault response
is in Hiccup mode.
• When the HIC/LATCH pin is pulled low (GND), the fault response is
in Latch-off mode.
In Hiccup mode, the device will stop switching when a fault
condition in Table 3 on page 34 is detected, and restart from
soft-start after 500ms (typical). This operation will be repeated
until fault conditions are completely removed.
In Latch-off mode, the device will stop switching when a fault
condition in Table 3 on page 34 is detected and PWM switching
being kept off even after fault conditions are removed. In
Latch-off status, the internal LDO is alive to keep PVCC voltage
regulated. By either toggling the EN pin or cycling VCC/PVCC
below the POR threshold will restart the system.
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FN8808.2
February 24, 2016