ISL78227 Datasheet, PDF (25/43 Pages) Intersil Corporation – 2-Phase Boost Controller with Integrated Drivers

ISL78227
300
250
tDT2
200
150
tDT1
100
50
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70
RD T (k)
FIGURE 50. DEAD TIME vs RDT, t_DT1 REFERS TO UG FALLING TO LG
RISING, t_DT2 REFERS TO LG FALLING TO UG RISING
PWM Control
The ISL78227 uses fixed frequency peak current mode control
architecture. As shown in Figure 3 on page 7 and the typical
schematic diagram, error amplifier (Gm1) compares the FB pin
voltage and reference voltage and generates a voltage loop error
signal at the COMP pin. This error signal is compared with the
current ramp signal (VRAMP) by the PWM comparator. The PWM
comparator output combined with fixed frequency clock signal
controls the SR flip-flop to generate the PWM signals (Refer to
“Peak Current Mode Control” on page 26).
OUTPUT VOLTAGE REGULATION LOOP
The resistor divider R_FB2 and R_FB1 from V_OUT to FB (Figure 4 on
page 8) can be selected to set the desired V_OUT. V_OUT can be
calculated by Equation 2.
V_OUT
=
V_REF

1

+
RR_{-----FF----BB----21-}
(EQ. 2)
Where in normal operation after soft-start, V_REF can be either
VREF_1.6V or VREF_TRK whichever is lower.
There are 3 inputs for the reference voltage for Gm1: soft-start
ramp SS, VREF_TRK and VREF_1.6V. The Gm1 uses the lowest
value among SS, VREF_TRK and VREF_1.6V. SS, VREF_TRK and
VREF_1.6V are valid for Gm1 during and after soft-start. In
general application, VREF_TRK is normally HIGH before soft-start
and SS normally ramps up from a voltage lower than VREF_TRK
and VREF_1.6V, in which case SS controls the output voltage
ramp-up during soft-start. After soft-start is complete, the user
can adjust VREF_TRK for the desired voltage. Since VREF_TRK is
valid before soft-start, to set VREF_TRK to be lower than SS can
make the SS ramp ineffective since Gm1 uses the lower
VREF_TRK voltage. In such a case, the VREF_TRK becomes the
real soft-start ramp that controls the output voltage ramp-up.
Digital/Analog Track Function
The TRACK input provides an external reference voltage to be
applied for the output voltage loop to follow, which is useful if the
user wants to change the output voltage as required. An example
is to employ envelope tracking technology in audio power
amplifier applications. The ISL78227 boost stage output is
powering the audio power amplifier stage input, where the boost
output tracks the music envelope signal applied at the TRACK
pin. Ultimately, higher system efficiency can be achieved.
The TRACK pin can accept either a digital signal or an analog
signal by configuring the ATRK/DTRK pin to be connected to
ground or VCC. Figure 51 on page 26 shows the track function
block diagram. VREF_TRK is fed into Gm1 as one of the
reference voltages. The Gm1 takes the lowest voltage of SS,
VREF_TRK and VREF_1.6V as the actual reference. When
VREF_TRK is the lowest voltage, it becomes the actual reference
voltage for Gm1 and the output voltage can be adjusted with
TRACK signal changes. Regarding the effective VREF_TRK range:
• There is no limit for the minimum voltage on the TRACK pin,
but note the lower reference voltage and the lower voltage
feedback regulation accuracy. Note the SS_DONE signal is
checking VREF_TRK ≥0.3V as one of the conditions (refer to
Figure 58 on page 29 and t₈-t₉ description on page 30). Also,
for the boost converter, the regulated output minimum voltage
is usually the input voltage minus the upper MOSFET’s body
diode drop, in which case, the corresponding voltage at FB
voltage is the minimum effective voltage for the VREF_TRK.
• The Gm1 takes the lowest voltage of SS, VREF_TRK and
VREF_1.6V as the actual reference. The maximum effective
range for VREF_TRK is determined by VREF_1.6V or SS signal,
whichever is lower. For example, after soft-start, when the SS
pin equals to 3.47V (typical), the maximum effective voltage
for VREF_TRK is 1.6V (VREF_1.6V).
When ATRK/DTRK = GND (DTRK mode), the TRACK pin accepts
digital signal inputs. VREF_TRK (as one of the references input
for the error amplifier Gm1) equals to the average duty cycle
value of the PWM signal’s at the TRACK pin. As shown in
Figure 51 on page 26, the MUX is controlled by the ATRK/DTRK
pin configurations. When ATRK/DTRK = GND, the MUX connects
the output of the Q1 and Q2 switch bridge to the input of a
2-stage RC filter (R₁, C₁, R₂ and C₂). The PWM signal at the
TRACK pin controls Q1 and Q2 to chop the 2.5V internal
reference voltage. The phase node of Q1 and Q2 is a PWM signal
with accurate 2.5V amplitude and duty cycle D, where D is the
input PWM duty cycle on the TRACK input pin. The RC filter
smooths out the PWM AC components and the voltage
VREF_TRK after the RC filter becomes a DC voltage equal to
2.5V*D:
V_REFTRK = 2.5  D
(EQ. 3)
According to Equation 3, the PWM signals’ amplitude at the TRACK
pin doesn’t affect the VREF_TRK accuracy and only the duty cycle
value changes the VREF_TRK value. In general, the VREF_TRK
reference accuracy is as good as the 2.5V reference. The built-in low
pass filter (R₁, C₁, R₂ and C₂) converts the PWM signal’s duty cycle
value to a low noise reference. The low pass filter has cutoff
frequency of 1.75kHz and a gain of -40dB at 400kHz. The 2.5V
Submit Document Feedback ₂₅
FN8808.2
February 24, 2016