ISL78227 Datasheet, PDF (4/43 Pages) Intersil Corporation – 2-Phase Boost Controller with Integrated Drivers

ISL78227
Functional Pin Description (Continued)
PIN NAME
IMON
TRACK
PGOOD
FSYNC
HIC/LATCH
DE/PHDRP
RBLANK
PLLCOMP
EN
CLKOUT
PIN #
6
7
8
9
10
11
12
13
14
15
DESCRIPTION
IMON is the average current monitor pin for the sum of the two phases’ inductor currents. It is used for average current limiting
and average current protection functions.
The sourcing current from the IMON pin is the sum of the two CSA’s outputs plus a fixed 17µA offset current. With each CSA
sensing individual phase’s inductor current, the IMON signal represents the sum of the two phases’ inductor currents and it is
the input current for the boost. A resistor in parallel with a capacitor are needed to be placed from IMON to ground. The IMON
pin output current signal builds up the average voltage signal representing the average current sense signals.
A constant average current limiting function and an average current protection are implemented based on the IMON signal.
1. Constant Current Control: A Constant Current (CC) control loop is implemented to control the IMON average current
signal equal to a 1.6V reference (VREF_CC), which ultimately limits the total input average current to a constant
level.
2. Average Current Protection: If the IMON pin voltage is higher than 2V, the part will go into either Hiccup or Latch-off fault
protection depending on the HIC/LATCH pin configuration.
Refer to “Average Current Sense for 2 Phases - IMON” on page 31 for more details.
External reference input pin for the IC output voltage regulation loop to follow. The input reference signal can be either digital
or analog signal selected by the ATRK/DTRK pin configuration.
If the TRACK function is not used, connect the TRACK pin to VCC and the internal VREF_1.6V will work as the reference. Refer
to “Digital/Analog Track Function” on page 25 for more details.
Provides an open-drain power-good signal. Pull up this pin with a resistor to this IC’s VCC for proper function. When the output
voltage is within OV/UV thresholds and soft-start is completed, the internal PGOOD open-drain transistor is open and PGOOD
is pulled HIGH. It will be pulled low once output UV/OV or input OV conditions are detected. Refer to “PGOOD Signal” on
page 30 for more details.
A dual-function pin for switching frequency setting and synchronization defined as follows:.
1. The PWM switching frequency can be programmed by a resistor R_FSYNC from this pin to ground. The PWM frequency
refers to a single-phase switching frequency in this datasheet. The typical programmable frequency range is 50kHz
to 1.1MHz.
2. The PWM switching frequency can also be synchronized to an external clock applied on the FSYNC pin. The FSYNC
pin detects the input clock signal’s rising edge that it is to be synchronized with. The typical detectable minimum
pulse width of the input clock is 20ns. The rising edge of LG1 is delayed by 35ns from the rising edge of the input
clock signal at the FSYNC pin. Once the internal clock is locked to the external clock, it will latch to the external clock.
If the external clock on the FSYNC pin is removed, the switching frequency oscillator will shut down. The part will
then detect PLL_LOCK fault and go to either Hiccup mode or Latch-off mode depending on the HIC/LATCHOFF pin
configuration. If the part is set in Hiccup mode, the part will restart with frequency set by R_FSYNC.
The typical synchronization frequency range is 50kHz to 1.1MHz.
The phase dropping mode is not allowed with external synchronization.
Refer to “Oscillator and Synchronization” on page 28 for more details.
This pin is used to select either Hiccup or Latch-off response to faults including output overvoltage (monitoring the FB
pin), output undervoltage (monitoring the FB pin, default inactive), V_IN overvoltage (monitoring the FB pin), peak
overcurrent protection (OC2_PEAK), and average current protection (monitoring the IMON pin), etc.
HIC/LATCH = HIGH to have Hiccup fault response.
HIC/LATCH = LOW to have Latch-off fault response. Either toggling the EN pin or recycling VCC POR resets the IC from
Latch-off status.
Refer to “Selectable Hiccup or Latch-Off Fault Response” on page 33 for more details.
This pin is used to select Diode Emulation mode (DE), Phase Dropping (PH_DROP) mode or Continuous Conduction Mode
(CCM). There are 3 configurable modes: 1. DE mode; 2. DE plus PH_DROP mode; 3. CCM mode.
Refer to Table 2 on page 33 for the 3 configurable options.
The phase dropping mode is not allowed with external synchronization.
A resistor from this pin to ground programs the blanking time for current-sensing after the PWM is ON (LG is ON). This
blanking time is also termed as t_MINON time meaning minimum ON-time once a PWM pulse is ON. Refer to “Minimum
On-Time (Blank Time) Consideration” on page 28 for the selection of R_BLANK.
This pin serves as the compensation node for the switching frequency clock’s PLL (Phase Lock Loop). A second order
passive loop filter connected between this pin and ground compensates the PLL loop. Refer to “Oscillator and
Synchronization” on page 28 for more details.
This pin is a threshold-sensitive enable input for the controller. When the EN pin is driven above 1.21V (typical), the
ISL78227 is enabled and the internal LDO is activated to power up PVCC followed by a start-up procedure. Driving the EN
pin below 0.95V will disable the IC and clear all fault states. Refer to “Enable” on page 30 for more details.
This pin outputs a clock signal with same frequency to one phase’s switching frequency. The rising edge signal on the CLKOUT
pin is delayed by 90° from the rising edge of LG1 of the same IC. With CLKOUT connected to the FSYNC pin of the second
ISL78227, a 4-phase interleaving operation can be achieved. Refer to “Oscillator and Synchronization” on page 28 for more
details.
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FN8808.2
February 24, 2016