ISL78227 Datasheet, PDF (36/43 Pages) Intersil Corporation – 2-Phase Boost Controller with Integrated Drivers

ISL78227
response, but with much more accurate control of the maximum
power the system has to handle at overloading conditions.
1. When fast changing overloading occurs, since V_IMON has
sensing delay of R_IMON*C_IMON, CC does not trip at initial
transient load current until it reaches the CC reference 1.6V.
OC1 will be triggered at the beginning to limit the inductor
peak current cycle-by-cycle.
2. After the delay of R_IMON*C_IMON, when V_IMON reaches the CC
reference 1.6V, CC control starts to work and limit duty cycles
to reduce the inductor current and keep the sum of the two
phases’ inductor currents being constant. The time constant
of the R_IMON*C_IMON is typically on the order of 10 times
slower than the voltage loop bandwidth so that the 2 loops
will not interfere with each other.
CC loop is active at the beginning of soft-start.
From Equations 13 and 14 on page 31, the constant current
control current threshold level for the total 2-phase boost input
current can be calculated by Equations 23.
I_INCC
=


-_R----_I-¹-_M--^.--⁶-_O----_N--
–
17

10^–6_
 _R-^R----_SS----_EE----_NT--  8A
(EQ. 23)
Average Overcurrent Fault (OC_AVG) Protection
The ISL78227 monitors the IMON pin voltage (which represents
the boost total input average current signal) to detect if Average
Overcurrent (OC_AVG) fault occurs. As shown in Figure 3 on
page 7, the comparator CMP_OCAVG compares V_IMON to 2V
threshold to detect this fault. This fault detection is active at the
beginning of soft-start (t₅ as shown in Figure 58 on page 29).
When V_IMON is higher than 2V, the OC_AVG fault is triggered.
ISL78227 will respond with fault protection actions to shut down
the PWM switching and enters either Hiccup or Latch-off mode
depending on HIC/LATCH pin configuration as described in
“Selectable Hiccup or Latch-Off Fault Response” on page 33 and
Table 3 on page 34.
Under the selection of Hiccup response for the OC_AVG fault,
when the IMON voltage falls down to be lower than the 2V
threshold, the device will return to normal switching through
Hiccup soft-start.
From Equations 13 and 14 on page 31, the OC_AVG fault’s
current threshold level for the total 2-phase boost input current
can be calculated by Equation 24.
I_INOCAVG
=


R^-----_I^--_M^--2---_O^----_N^--
–
17

10^–6_
 _R-^R----_SS----_EE----_NT--  8A
(EQ. 24)
INTERNAL DIE OVER-TEMPERATURE PROTECTION
The ISL78227 PWM will be disabled if the junction temperature
reaches +160°C (typical) while the internal LDO is alive to keep
PVCC/VCC biased (VCC connected to PVCC). A +15°C hysteresis
ensures that the device will restart with soft-start when the
junction temperature falls below +145°C (typical).
Internal 5.2V LDO
The ISL78227 has an internal LDO with input at VIN and a fixed
5.2V/100mA output at PVCC. The internal LDO tolerates an input
supply range of VIN up to 55V (60V absolute maximum). A 10µF,
10V or higher X7R type of ceramic capacitor is recommended
between PVCC to GND. At low VIN operation when the internal
LDO is saturated, the dropout voltage from the VIN pin to the
PVCC pin is typically 0.3V under 80mA load at PVCC as shown in
the “Electrical Specifications” table on page 9. This is one of the
constraints to estimate the required minimum VIN voltage.
The output of this LDO is mainly used as the bias supply for the
gate drivers. With VCC connected to PVCC as in the typical
application, PVCC also supplies other internal circuitry. To provide
a quiet power rail to the internal analog circuitry, it is
recommended to place an RC filter between PVCC and VCC. A
minimum of 1µF ceramic capacitor from VCC to ground should
be used for noise decoupling purpose. Since PVCC is providing
noisy drive current, a small resistor like 10Ω or smaller between
the PVCC and VCC helps to prevent the noises interfering from
PVCC to VCC.
Figure 62 shows the internal LDO’s output voltage (PVCC)
regulation versus its output current. The PVCC will drop to 4.5V
(typical) when the load is 195mA (typical) because of the LDO
current limiting circuits. When the load current further increases,
the voltage will drop further and finally enter current foldback
mode where the output current is clamped to 100mA (typical). At
the worst case when LDO output is shorted to ground, the LDO
output is clamped to 100mA.
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.00
0.05
0.10
0.15
IOUT_PVCC (A)
0.20
0.25
FIGURE 62. INTERNAL LDO OUTPUT VOLTAGE vs LOAD
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February 24, 2016