English
Language : 

ISL78227 Datasheet, PDF (29/43 Pages) Intersil Corporation – 2-Phase Boost Controller with Integrated Drivers
◁
ISL78227
cycle is smallest at tMINON and CBOOTx is charged by PVCC via
DBOOTx with short duration of tMINON minus the delay to pull
phase low. If such operation is required, especially when a
large MOSFET with large Qg is used to support heavy load
application, larger tMINON can be programmed with the
resistor at the RBLANK pin to ensure CBOOTx can be
sufficiently charged during minimum duty cycle operation.
Please refer to Figure 57 for the selection of RBLANK resistor
and tMINON time. A 5kΩ resistor is recommended as the
minimum RBLANK resistor.
500
450
400
350
300
250
200
150
100
50
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70
RBLANK (k)
FIGURE 57. tMINON vs RBLANK
Operation Initialization and Soft-Start
Prior to converter initialization, the EN pin voltage needs to be
higher than its rising threshold and the PVCC/VCC pin needs to be
higher than the rising POR threshold. When these conditions are
met, the controller begins initialization and soft-start. Figure 58
shows the ISL78227 internal start-up timing diagram from the
power-up to soft-start.
1.2V
EN
POR_R PVCC/VCC
PLLCOMP
CLKOUT
LG
UG
COMP
VFB
COMP_Ramp_Offset
SS
PGOOD
t1 t2 t3
t4t5 t6
t7
t8 t9
FIGURE 58. CIRCUIT INITIALIZATION AND SOFT-START
Assuming input voltage is applied to the VIN pin before t1 and VCC
is connected to PVCC, as shown on Figure 58, the descriptions for
start-up procedure is elaborated in the following:
t1 - t2: The enable comparator holds the ISL78227 in shutdown
until the VEN rises above 1.2V (typical) at the time of t1. During
t1 - t2 VPVCC/VCC will gradually increase and reaches the internal
Power-on Reset (POR) rising threshold 4.5V (typical) at t2.
t2 - t3: During t2 - t3, the ISL78227 will go through a
self-calibration process to detect certain pin configurations
(HIC/LATCH, DE/PHDRP, ATRK/DTRAK) to latch in the selected
operation modes. The time duration for t2 - t3 is typically 195µs.
t3 - t4: During this period, the ISL78227 will wait until the internal
PLL circuits are locked to the preset oscillator frequency. When
PLL locking is achieved at t4, the oscillator will generate output
at the CLK_OUT pin. The time duration for t3 - t4 depends on the
PLLCOMP pin configuration. The PLL is compensated with a
series resistor-capacitor (RPLL and CPLL1) from the PLLCOMP pin
to GND and a capacitor (CPLL2) from PLLCOMP to GND. At
300kHz switching frequency, typical values are RPLL = 3.24kΩ,
CPLL1 = 6.8nF, CPLL2 = 1nF. With this PLLCOMP compensation,
the time duration for t3 - t4 is around 0.7ms.
t4 - t5: The PLL locks the frequency t4 and the system is
preparing to soft-start. The ISL78227 has one unique feature to
prebias the SS pin voltage to be equal to VFB during t4 - t5, which
is around 50µs.
t5 - t6: At t5 the soft-start ramps up at the SS pin (VSSPIN) and the
COMP voltage starts to ramp-up as well. Drivers are enabled but
not switching during t5 - t6 since the COMP is still below the
current sense ramp offset. The device operates in diode
emulation mode during soft-start period t5 - t8. The slew rate of
Submit Document Feedback 29
FN8808.2
February 24, 2016
 ▷