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ISL78227 Datasheet, PDF (41/43 Pages) Intersil Corporation – 2-Phase Boost Controller with Integrated Drivers
ISL78227
FIGURE 67. RECOMMENDED LAYOUT PATTERN FOR VIAS IN THE
IC BOTTOM PAD
7. Place the 10µF decoupling ceramic capacitor at the PVCC pin
and as close as possible to the IC. Put multiple vias close to
the ground pad of this capacitor.
8. Place the 1µF decoupling ceramic capacitor at the VCC pin
and as close as possible to the IC. Put multiple vias close to
the ground pad of this capacitor.
9. Keep the bootstrap capacitors as close as possible to the IC.
10. Keep the driver traces as short as possible and with relatively
large width (25mil to 40mil is recommended), and avoid
using via or minimal number of vias in the driver path to
achieve the lowest impedance.
11. Place the current sense setting resistors and the filter
capacitors (shown as RSETxB, RBIASxB and CISENx in Figure 60
on page 31) as close as possible to the IC. Keep each pair of
the traces close to each other to avoid undesired switching
noise injections.
12. The current-sensing traces must be laid out very carefully
since they carry tiny signals with only tens of mV.
For the current-sensing traces close to the power sense resistor
(RSENx), the layout pattern shown in Figure 68 is recommended.
Assuming the RSENx is placed in the top layer (red), route one
current sense connection from the middle of one RSENx pad in
the top layer under the resistor (red trace). For the other current-
sensing trace, from the middle of the other pad on RSENx in top
layer, after a short distance, via down to the second layer and
route this trace right under the top layer current sense trace.
13. Keep the current-sensing traces far from the noisy traces like
gate driving traces (LGx, UGx and PHx), phase nodes in power
stage, BOOTx signals, output switching pulse currents, driving
bias traces and input inductor ripple current signals, etc.
FIGURE 68. RECOMMENDED LAYOUT PATTERN FOR CURRENT
SENSE TRACES REGULATOR
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FN8808.2
February 24, 2016