ISL78227 Datasheet, PDF (5/43 Pages) Intersil Corporation – 2-Phase Boost Controller with Integrated Drivers

ISL78227
Functional Pin Description (Continued)
PIN NAME
BOOT2
UG2
PH2
LG2
PGND
PVCC
LG1
PH1
UG1
BOOT1
VIN
ISEN1N
ISEN1P
ISEN2N
ISEN2P
ATRK/DTRK
RDT
SGND
PIN #
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
-
DESCRIPTION
This pin provides bias voltage to the Phase 2 high-side MOSFET driver. A bootstrap circuit is used to create a voltage suitable
to drive the external N-channel MOSFET. A 0.47µF ceramic capacitor in series with a 1.5Ω resistor are recommended between
the BOOT2 and PH2 pins. In the typical configuration, PVCC is providing the bias to BOOT2 through a fast switching diode.
In applications where a high-side driver is not needed (standard boost application for example), BOOT2 is recommended
to be connected to ground. The ISL78227 IC can detect BOOT2 being grounded during start-up and both the Phase 1 and
Phase 2 high-side drivers will be disabled. In addition, PH1 and PH2 should also be tied to ground.
Phase 2 high-side gate driver output. This output can be disabled by tying either BOOT1 and PH1 to ground or BOOT2 and
PH2 to ground.
Connect this pin to the source of the Phase 2 high-side MOSFETs and the drain of the low-side MOSFETs. This pin
represents the return path for the Phase 2 high-side gate drive.
Phase 2 low-side gate driver output. It should be connected to the Phase 2 low-side MOSFETs’ gates.
Provides the return path for the low-side MOSFET drivers. This pin carries a noisy driving current and traces connecting
from this pin to the low-side MOSFET source and PVCC decoupling capacitor ground pad should be as short as possible.
All the sensitive analog signal traces should not share common traces with this driver return path. Connect this pin to
the ground copper plane (wiring away from the IC instead of connecting through the IC bottom PAD) through several vias
as close as possible to the IC.
Output of the internal linear regulator that provides bias for the low-side driver, high-side driver (PVCC connected to BOOTx
through diodes) and VCC bias (PVCC and VCC are typically connected through a small resistor like 10Ω or smaller, which helps
to filter out the noises from PVCC to VCC). The PVCC operating range is 4.75V to 5.5V. A minimum 10µF decoupling ceramic
capacitor should be used between PVCC and PGND. Refer to “Internal 5.2V LDO” on page 36 for more details.
Phase 1 low-side gate driver output. It should be connected to the Phase 1 low-side MOSFETs’ gates.
Connect this pin to the source of the Phase 1 high-side MOSFETs and the drain of the low-side MOSFETs. This pin
represents the return path for the Phase 1 high-side gate drive.
Phase 1 high-side MOSFET gate drive output. This output can be disabled by tying either BOOT1 and PH1 to ground or
BOOT2 and PH2 to ground.
This pin provides bias voltage to the Phase 1 high-side MOSFET driver. A bootstrap circuit is used to create a voltage suitable
to drive the external N-channel MOSFET. A 0.47µF ceramic capacitor in series with a 1.5Ω resistor are recommended between
BOOT1 and PH1 pins. In typical configuration, PVCC is providing the bias to BOOT1 through a fast switching diode.
In applications where a high-side driver is not needed (for example, standard boost application), the BOOT1 is
recommended to be connected to ground. The ISL78227 IC can detect BOOT1 being grounded during start-up and both
the Phase 1 and Phase 2 high-side drivers will be disabled. In addition, PH1 and PH2 should also be tied to ground.
Connect supply rail to this pin. Typically, connect boost input voltage to this pin. This pin is connected to the input of the internal
linear regulator, generating the power necessary to operate the chip. The DC voltage applied to VIN should not exceed 55V
during normal operation. VIN can withstand transients up to 60V, but in this case, the device's overvoltage protection will stop
it from switching to protect itself. Refer to “Input Overvoltage Fault Protection” on page 34 for more details.
The ISEN1N pin is the negative potential input to the Phase 1 current sense amplifier. This amplifier continuously senses
the Phase 1 inductor current through a power current sense resistor in series with the inductor. The sensed current signal
is used for current mode control, peak current limiting, average current limiting and diode emulation.
The ISEN1P pin is the positive potential input to the Phase 1 current sense amplifier.
The ISEN2N pin is the negative potential input to the Phase 2 current sense amplifier. This amplifier continuously senses
the Phase 2 inductor current through a power current sense resistor in series with the inductor. The sensed current signal
is used for current mode control, peak current limiting, average current limiting and diode emulation.
The ISEN2P pin is the positive phase input to the Phase 2 current sense amplifier.
The logic input pin to select the input signal format options for the TRACK pin. Pull this pin HIGH for the TRACK pin to
accept analog input signals. Pull this pin LOW for the TRACK pin to accept digital input signals. Refer to “Digital/Analog
Track Function” on page 25 for more details.
A resistor connected from this pin to ground programs the dead times between UGx OFF to LGx ON and LGx OFF to UGx
ON to prevent shoot-through. Please refer to “Driver Configuration” on page 24 for the selection of RDT.
Signal ground bottom pad for the internal sensitive analog circuits to be referred to, also serves as thermal pad. Connect
this pad to large ground plane. Put multiple vias (as many as possible) in this pad connecting to the ground copper plane to
help reduce the IC’s _JA. In layout power flow planning, avoid having the noisy high frequency pulse current flow through
the SGND area.
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FN8808.2
February 24, 2016