ISL78227 Datasheet, PDF (40/43 Pages) Intersil Corporation – 2-Phase Boost Controller with Integrated Drivers

ISL78227
COMPENSATOR DESIGN
Generally simple Type-2 compensator can be used to stabilize
the system. In the actual application, however, an extra phase
margin will be provided by a Type-3 compensator.
Vo
RFB2
RFB1
R1
C1
He1(s)
FB
+
Gm
-
Vc
COMP
VREF
RCP
CCP1
CCP2
He2(s)
ROEA
FIGURE 66. TYPE-3 COMPENSATOR
The transfer function at the error amplifier and its compensation
network can be expressed as Equation 36.
H_e2s = _V--^V---_F-^C--_B-- = g_m  Z_COMP =
(EQ. 36)
gm -₁----+-----_s----_--_R-----_C----_P-----_C----_C-----_P-----₁-----+-----_R----_O-----_E-----^_A--¹--_---_C^+----_C-^s---^R-_P----^C-₁----^P-+---^C-_C----^C-_C----^P-_P---¹-₂---^-_--^R_----+^O-----_CE----_C-^A----_P-----₂----_C----_C-----_P-----₁---_R-----_C-----_P----_R-----_O-----_E-----_A-----_S----₂--
If R_OEA>>R_CP, C_CP1>>C_CP2, and R_OEA = infinite, the equation
can be simplified as shown in Equation 37:
H_e2s
=
g_m  _s-----_---_C-----_C----¹_P----₁-+---_-^s--_---₁^---^R-+----^C-_s---^P--_---^_R---^C-_C---^C--_P---^P--_-¹--_C----_C----_P----₂----_
=
1 + ----^s-----
-^--_s--¹-  -₁----+-------^_------s--^z_------²_--
_p2
(EQ. 37)
Where,
_p2 = _C----^g-_C---^m-_P----₁-
_z2 = _R-----_C----_P-----_-¹--_C-----_C----_P----₁-
_p3 = -_R----_C----_P-----_-¹--_C-----_C----_P----₂-
If Type-3 compensation is needed, the transfer function at the
feedback resistor network is:
H_e1S
=
-_R----_F----_B--^R--₁---^F-+--^B---_R-¹---_F----_B----₂-

1 + ----^s-----
1^{-----+-------}------^s--^z------¹--
_p1
(EQ. 38)
Where,
_z1 = -_C----₁-----_---_--_R-----_F--¹-_B----₂----+-----_R-----₁----_
_p1 = _C-----₁----_----_R---------F--------_B--------₂--------_------_R----------_F------_B--------₁--_R--------+--_F------_B-_R-----¹--₂--_F-------+-_B-------_2-R--------_--_F----_R---_B------1-1--------+----------_R--------_F--------_B--------₁--------_------_R----------₁--
The total transfer function with compensation network and gain
stage will be expressed:
G_opens = G_vcvos  H_e1s  H_e2s
(EQ. 39)
Use f = ω/2π to convert the pole and zero expressions to
frequency domain, and from Equations 33, 38 and 39, select the
compensator’s pole and zero locations.
In general, as described earlier, a type-2 compensation is
enough. Typically the crossover frequency is set 1/5 to 1/3 of the
ω_RHZ frequency. For the compensator as general rule, set
ω_p2/2π at very low end frequency; set ω_z2/2π at 1/5 of the
crossover frequency; set ω_p3/2π at the ESR zero or the RHZ
frequency ω_RHZ/2π, whichever is lower.
VCC Input Filter
To provide a quiet power rail to the internal analog circuitry, it is
recommended to place an RC filter between PVCC and VCC. A
10Ω resistor between PVCC and VCC and at least 1µF ceramic
capacitor from VCC to GND are recommended.
Current Sense Circuit
To set the current sense resistor, the voltage across the current
sense resistor should be limited to within ±0.3V. In a typical
application, it is recommended to set the voltage across the
current sense resistor in range around 30mV to 100mV for the
typical load current condition.
Layout Considerations
For DC/DC converter design, the PCB layout is a very important to
ensure the desired performance.
1. Place input ceramic capacitors as close as possible to the IC's
VIN and PGND/SGND pins.
2. Place the output ceramic capacitors as close as possible to
the power MOSFETs. Keep this loop (output ceramic capacitor
and MOSFETs for each phase) as small as possible to reduce
voltage spikes induced by the trace parasitic inductances
when MOSFETs switching ON and OFF.
3. Place the output aluminum capacitors close to the power
MOSFETs.
4. Keep the phase node copper area small but large enough to
handle the load current.
5. Place the input aluminum and some ceramic capacitors close
to the input inductors and power MOSFETs.
6. Place multiple vias under the bottom pad of the IC. The
bottom pad should be connected to the ground copper plane
with as large an area as possible in multiple layers to
effectively reduce the thermal impedance. Figure 67 shows
the layout example for vias in the IC bottom pad.
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FN8808.2
February 24, 2016