ISL78227 Datasheet, PDF (13/43 Pages) Intersil Corporation – 2-Phase Boost Controller with Integrated Drivers

ISL78227
Electrical Specifications Refer to Figure 3 on page 7 and Typical Application Schematics (page 8). Operating conditions unless
otherwise noted: V_IN = 12V, V_PVCC = 5.2V and V_VCC = 5.2V, T_A = -40°C to +125°C (Note 7). Typicals are at T_A = +25°C. Boldface limits apply across
the operating temperature range, -40°C to +125°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
(Note 6) TYP (Note 6) UNIT
AVERAGE CONSTANT CURRENT CONTROL LOOP
IMON Current Accuracy
V_RSENx = 30mV, R_SETx = 665Ω (0.1%), with
ISENxP/N pins biased at 4V or 55V
common-mode voltage
27.0
28.3
29.5 µA
IMON Offset Current
V_RSENx = 0V, R_SET = 665Ω (0.1%), with
ISENxP/N pins biased at 4V or 55V
common-mode voltage
16
17
18 µA
Constant Current Control Reference Accuracy
VREF_CC Measure the IMON pin
1.575 1.600 1.625 V
AVERAGE OVERCURRENT FAULT PROTECTION OC_AVG, (Refer to “Average Overcurrent Fault (OC_AVG) Protection” on page 36 for details)
OC_AVG Fault Threshold at the IMON Pin
1.9
2.0
2.1
V
OC_AVG Fault Trip Delay
1
µs
GATE DRIVERS
UG Source Resistance
UG Source Current
UG Sink Resistance
UG Sink Current
LG Source Resistance
LG Source Current
LG Sink Resistance
LG Sink Current
UG to PH Internal Resistor
R_{UG_SOURCE} 100mA source current, V_BOOT - V_PH = 4.4V
1.2
Ω
I_{UG_SOURCE} V_UG - V_PH = 2.5V, V_BOOT - V_PH = 4.4V
2
A
R_{UG_SINK} 100mA sink current, V_BOOT - V_PH = 4.4V
0.6
Ω
I_{UG_SINK} V_UG - VPH = 2.5V, V_BOOT - V_PH = 4.4V
2.0
A
R_{LG_SOURCE} 100mA source current, PVCC = 5.2V
1.2
Ω
I_{LG_SOURCE} V_LG - PGND = 2.5V, PVCC = 5.2V
2.0
A
R_{LG_SINK} 100mA sink current, PVCC = 5.2V
0.55
Ω
I_{LG_SINK} V_LG - PGND = 2.5V, PVCC = 5.2V
3
A
50
kΩ
LG to PGND Internal Resistor
50
kΩ
BOOT-PH UVLO Detection Threshold
2.8
3.0
3.2
V
BOOT-PH UVLO Detection Threshold Hysteresis
0.09
0.15
0.22 V
Dead Time Delay - UG Falling to LG Rising
t_DT1
C_UG = C_LG = OPEN, R_DT = 10k (0.1%)
55
70
85
ns
Dead Time Delay - LG Falling to UG Rising
t_DT2
C_UG = C_LG = OPEN, R_DT = 10k (0.1%)
65
80
95
ns
Dead Time Delay - UG Falling to LG rising
t_DT1
C_UG = C_LG = OPEN, R_DT = 18.2kΩ (0.1%)
85
100
115 ns
Dead Time Delay - LG Falling to UG Rising
t_DT2
C_UG = C_LG = OPEN, R_DT = 18.2kΩ (0.1%)
95
110
125 ns
Dead Time Delay - UG Falling to LG Rising
t_DT1
C_UG = C_LG = OPEN, R_DT = 50kΩ (0.1%)
185
210
240 ns
Dead Time Delay - LG Falling to UG Rising
t_DT2
C_UG = C_LG = OPEN, R_DT = 50kΩ (0.1%)
205
230
260 ns
Dead Time Delay - UG Falling to LG Rising
t_DT1
C_UG = C_LG = OPEN, R_DT = 64.9kΩ (0.1%)
235
265
295 ns
Dead Time Delay - LG Falling to UG Rising
t_DT2
C_UG = C_LG = OPEN, R_DT = 64.9kΩ (0.1%)
260
290
320 ns
OUTPUT OVERVOLTAGE DETECTION/PROTECTION MONITOR THE FB PIN, (Refer to “Output Overvoltage Fault Protection” on page 34 for details)
FB Overvoltage Rising Trip Threshold
V_{FBOV_RISE} Percentage of VREF_1.6V
(Selectable Hiccup/Latch-off response)
118
120
122 %
FB Overvoltage Falling Recovery Threshold
V_{FBOV_FALL} Percentage of VREF_1.6V
(Selectable Hiccup/Latch-off response)
114
116
118 %
Overvoltage Threshold Hysteresis
4
%
FB Overvoltage Trip Delay
1
µs
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FN8808.2
February 24, 2016