X3102 Datasheet, PDF (30/32 Pages) Intersil Corporation – 3 Cell Li-Ion Battery Protection and Monitor IC

X3102
CS
SCK
SI
0123456789
20 21 22 23 24 25 26 27 28 29 30 31
EEREAD Instruction
(1 Byte)
Byte Address (2 Byte)
15 14
3210
Data Out
High Impedance
SO
76543210
FIGURE 21. EEPROM (EEREAD) READ OPERATION SEQUENCE
CS
SCK
SI
SO
0123456789
20 21 22 23
WCFIG Instruction
(1 BYTE)
High Impedance
Configuration
Register Data
15 14
3210
(2 BYTE)
FIGURE 22. WRITE CONFIGURATION REGISTER (WCFIG) OPERATION SEQUENCE
CS
SCK
SI
SO
0123456789
18 19 20 21 22 23
WCNTR Instruction
(1 Byte)
High Impedance
Control
Register Data
15 14
543210
(2 Byte)
Control
Bits
Old Control Bits
New Control Bits
FIGURE 23. WRITE CONTROL REGISTER (WCNTR) OPERATION SEQUENCE
Write Control Register (WCNTRL)
The Write Control Register (WCNTRL) instruction updates
the contents of the volatile Control Register. This command
sets the status of the FET control pins, the cell balancing
outputs, the current sense gain and external entry to the
sleep mode. Since this instruction controls a volatile
register, no other commands are required and there is no
delay time needed after the instruction, before subsequent
commands. The operation of the WCNTRL command is
shown in Figure 23.
30
FN8246.0
December 22, 2004