X3102 Datasheet, PDF (3/32 Pages) Intersil Corporation – 3 Cell Li-Ion Battery Protection and Monitor IC

X3102
Pin Names (Continued)
PIN SYMBOL
DESCRIPTION
15
AO
Analog multiplexer output. The analog output pin is used to externally monitor various battery parameter voltages. The
voltages which can be monitored at AO (See section “Analog Multiplexer Selection” on page 25) are:
– Individual cell voltages
– Voltage across the current sense resistor (R_SENSE)^. This voltage is amplified with a gain set by the user in the control register
(See section “Current Monitor Function” on page 25.)
The analog select pins AS0–AS2 select the desired voltage to be monitored on the AO pin.
16
AS0 Analog output select pin 0. These pins select which voltage is to be multiplexed to the output AO (See section “Sleep Control
(SLP)” on page 17 and section “Current Monitor Function” on page 25)
17
AS1 Analog output select pin 1. These pins select which voltage is to be multiplexed to the output AO (See section “Sleep Control
(SLP)” on page 17 and section “Current Monitor Function” on page 25)
18
AS2 Analog output select pin 2. These pins select which voltage is to be multiplexed to the output AO (See section “Sleep Control
(SLP)” on page 17 and section “Current Monitor Function” on page 25)
19
SI
Serial data input. SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the device are input on
this pin.
20
SO
Serial data output. SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked
out by the falling edge of the serial clock. While CS is HIGH, SO will be in a High Impedance state.
Note: SI and SO may be tied together to form one line (SI/SO). In this case, all serial data communication with the X3102 is
undertaken over one I/O line. This is permitted ONLY if no simultaneous read/write operations occur.
21
SCK Serial data clock input. The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data
present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge
of the clock input.
22
CS
Chip select input pin. When CS is HIGH, the device is deselected and the SO output pin is at high impedance. CS LOW
enables the SPI serial bus.
23 OVP/LMON Over-charge Voltage Protection output/Load Monitor output. This one pin performs two functions depending upon the
present mode of operation of the X3102.
Over-charge Voltage Protection (OVP)
This pin controls the switching of the battery pack charge FET. This power FET is a P-channel device. As such, cell charge is
possible when OVP/LMON=V_SS, and cell charge is prohibited when OVP/LMON=V_CC. In this configuration the X3102 turns
off the charge voltage when the cells reach the over-charge limit. This prevents damage to the battery cells due to the
application of charging voltage for an extended period of time (See section “Over-charge Protection” on page 19).
Load Monitor (LMON)
In Overcurrent Protection mode, a small test current (7.5µA typ.) is passed out of this pin to sense the load resistance. The
measured load resistance determines whether or not the X3102 returns from an overcurrent protection mode (See section
“Overcurrent Protection” on page 23).
24 UVP/ Over-discharge protection output/Overcurrent protection output. Pin UVP/OCP controls the battery cell discharge via an
OCP external power FET. This P-channel FET allows cell discharge when UVP/OCP=Vss, and prevents cell discharge when
UVP/OCP=Vcc. The X3102 turns the external power FET off when the X3102 detects either:
Over-discharge Protection (UVP)
In this case, pin 24 is referred to as “Over-discharge (Undervoltage) protection (UVP)” (See section “Over-discharge Protection”
on page 20). UVP/OCP turns off the FET to prevent damage to the battery cells by being discharged to excessively low
voltages.
Overcurrent protection (OCP)
In this case, pin 24 is referred to as “Overcurrent protection (OCP)” (See section “Overcurrent Protection” on page 23).
UVP/OCP turns off the FET to prevent damage to the battery pack caused by excessive current drain (e.g. as in the case of a
surge current resulting from a stalled disk drive).
25
RGO Voltage regulator output pin. This pin is an input that connects to the collector of an external PNP transistor. The voltage at
this pin is the regulated output voltage, but it also provides the feedback voltage for the regulator and the operating voltage for
the device.
26
RGC Voltage regulator control pin. This pin connects to the base of an external PNP transistor and controls the transistor turn on.
27
RGP Voltage regulator protection pin. This pin is an input that connects to the emitter of an external PNP transistor and an external
current limit resistor and provides a current limit voltage.
28
VCC Power supply. This pin is provides the voltage for FET control, regulator operation, and wake-up circuits.
3
FN8246.0
December 22, 2004