X3102 Datasheet, PDF (28/32 Pages) Intersil Corporation – 3 Cell Li-Ion Battery Protection and Monitor IC

X3102
Write Enable/Write Disable (WREN/WRDI)
Any write to a nonvolatile array or register, requires the
WREN command be sent prior to the write command. This
command sets an internal latch allowing the write operation to
proceed. The WRDI command resets the internal latch if the
system decides to abort a write operation. See Figure 17.
CS
SCK
01234567
Instruction
(1 Byte)
WREN
SI
High Impedance
SO
WRDI
FIGURE 17. EEPROM WRITE ENABLE LATCH (WREN/WRDI)
OPERATION SEQUENCE
EEPROM Write Sequence (EEWRITE)
Prior to any attempt to write data into the EEPROM of the
X3102, the “Write Enable” latch must first be set by issuing
the WREN instruction (See Table 30 and Figure 17). CS is
first taken LOW. Then the WREN instruction is clocked into
the X3102. After all eight bits of the instruction are
transmitted, CS must then be taken HIGH. If the user
continues the write operation without taking CS HIGH after
issuing the WREN instruction, the write operation will be
ignored.
To write data to the EEPROM memory array, the user issues
the EEWRITE instruction, followed by the 16 bit address and
the data to be written. Only the last 9 bits of the address are
used and bits [15:9] are specified to be zeroes. This is
minimally a thirty-two clock operation. CS must go LOW and
remain LOW for the duration of the operation. The host may
continue to write up to 16 bytes of data to the X3102. The
only restriction is the 16 bytes must reside on the same
page. If the address counter reaches the end of the page
and the clock continues, the counter will “roll over” to the first
address of the page and overwrite any data that may have
been previously written.
For a byte or page write operation to be completed, CS can
only be brought HIGH after bit 0 of the last data byte to be
written is clocked in. If it is brought HIGH at any other time,
the write operation will not be completed. Refer to Figure 18
and Figure 19 for detailed illustration of the write sequences
and time frames in which CS going HIGH are valid.
EEPROM Read Status Operation (EEREAD STAT)
If there is not a nonvolatile write in progress, the EEREAD
STAT instruction returns the IDLock byte from the IDLock
register which contains the IDLock bits IDL2-IDL0 (Table 29).
The IDLock bits define the IDLock condition (Table 28). The
other bits are reserved and will return ‘0’ when read.
If a nonvolatile write to the EEPROM (i.e. EEWRITE
instruction) is in progress, the EEREAD STAT returns a
HIGH on SO. When the nonvolatile write cycle in the
EEPROM is completed, the status register data is read out.
Clocking SCK is valid during a nonvolatile write in progress,
but is not necessary. If the SCK line is clocked, the pointer to
the status register is also clocked, even though the SO pin
shows the status of the nonvolatile write operation (See
Figure 20).
CS
SCK
SI
0123456789
20 21 22 23 24 25 26 27 28 29 30 31
EEWRITE Instruction
(1 Byte)
Byte Address (2 Byte)
15 14
3210
Data Byte
76543210
High Impedance
SO
FIGURE 18. EEPROM BYTE WRITE (EEWRITE) OPERATION SEQUENCE
28
FN8246.0
December 22, 2004