X3102 Datasheet, PDF (22/32 Pages) Intersil Corporation – 3 Cell Li-Ion Battery Protection and Monitor IC

X3102
TABLE 22. OVER-DISCHARGE PROTECTION MODE—EVENT DIAGRAM DESCRIPTION
EVENT
EVENT DESCRIPTION
[0,1)
• Charge FET is ON (OVP/LMON = V_SS)
• Discharge FET is ON (UVP/OCP = V_SS), and hence battery cells are permitted to discharge.
• All cell voltages (VCELL₁–VCELL₄) are above the Over-discharge threshold voltage (V_UV).
• The device is in normal operation mode (i.e. not in a protection mode).
[1]
• The voltage of one or more of the battery cells (V_CELL), falls below V_UV.
• The internal over-discharge detection delay timer begins counting down.
• The device is still in normal operation mode
(1,2)
[2]
• The internal over-discharge detection delay timer continues counting for T_UV seconds.
• The internal over-discharge detection delay timer times out, AND V_CELL is still below V_UV.
• The internal over-discharge sense circuitry switches the discharge FET OFF (UVP/OCP = Vcc).
• The charge FET is switched OFF (OVP/LMON = V_CC).
• The device has now entered over-discharge protection mode.
• At the same time, the device enters sleep mode (See section “Voltage Regulator” on page 26).
(2,3)
• While device is in sleep (in over-discharge protection) mode:
• The power to ALL internal circuits is switched OFF limiting power consumption to less than 1µA.
• The output of the 5VDC voltage regulator (RGO) is 0V.
• Access to the X3102 via the SPI port is NOT possible.
[3] • Return from sleep mode (but still in over-discharge protection mode):
• Vcc rises above the “Return from Sleep mode threshold Voltage” (V_SLR)—This would normally occur in the case that the battery
pack was connected to a charger. The X3102 is now powered via P+/P-, and not the battery pack cells.
• Power is returned to ALL internal circuitry
• 5VDC output is returned to the regulator output (RGO).
• Access is enabled to the X3102 via the SPI port.
• The status of the discharge FET remains OFF (It is possible to change the status of UVPC in the control register, although it will
have no effect at this time).
(3,4)
If the cell charge enable function is • The X3102 initiates a reset operation that takes the longer of T_OV+200ms or T_UV+200ms to
switched ON
complete. Do not write to the FET control bits during this time.
AND V_CELL > V_CE
OR
Charge enable function is
switched OFF
• The charge FET is switched On (OVP/LMON = Vss) by the microcontroller by writing a “1” to
the OVPC bit in the control register.
• The battery cells now receive charge via the charge FET and diode D1 across the discharge
FET (which is OFF).
• The X3102 monitors the V_CELL voltage to determine whether or not it has risen above V_UVR.
If the cell charge enable function is • Charge/discharge of the battery cells via P+ is no longer permitted (Charge FET and discharge
switched ON
FET are held OFF).
AND
V_CELL < V_CE
• (Charging may re-commence only when the Cell Charge Enable function is switched OFF -
See Sections: “Configuration Register” page 4, and “Sleep mode” page 17.)
[4]
• The voltage of all of the battery cells (V_CELL), have risen above V_UVR.
• The internal Over-discharge release timer begins counting down.
• The X3102 is still in over-discharge protection mode.
(4,5)
• The internal over-discharge release timer continues counting for t_UVR seconds.
• The X3102 should be in monitor mode (AS2:AS0 not all low) for recovery time based on t_UVR. Otherwise recovery is based on two
successive samples about 120ms apart.
[5]
• The internal over-discharge release timer times out, AND V_CELL is still above V_UVR.
• The device returns from over-discharge protection mode, and is now in normal operation mode.
• The Charger voltage can now drop below VSLR and the X3102 will not go back to sleep.
• The discharge FET is can now be switched ON (UVP/OCP = V_SS) by the microcontroller by writing a “1” to the UVPC bit of the
control register.
• The status of the charge FET remains unaffected (ON)
• The battery cells continue to receive charge via the charge FET and discharge FET (both ON).
22
FN8246.0
December 22, 2004