X3102 Datasheet, PDF (17/32 Pages) Intersil Corporation – 3 Cell Li-Ion Battery Protection and Monitor IC

X3102
bytes respectively). The functions that can be manipulated
by the Control Register are shown in Table 12.
TABLE 12. CONTROL REGISTER FUNCTIONALITY
BIT(S) NAME
FUNCTION
0–4
– (don’t care)
5, 6
0, 0 Reserved—write 0 to these locations.
7
SLP Select sleep mode.
8,9 CSG1, Select current sense voltage gain
CSG0
10 OVPC OVP control: switch pin OVP = V_CC/V_SS
11 UVPC UVP control: switch pin UVP = V_CC/V_SS
12 CBC1 CB1 control: switch pin CB1 = V_CC/V_SS
13 CBC2 CB2 control: switch pin CB2 = V_CC/V_SS
14 CBC3 CB3 control: switch pin CB3 = V_CC/V_SS
15
– (don’t care)
Sleep Control (SLP)
Setting the SLP bit to ‘1’ forces the X3102 into the sleep
mode, if V_CC < V_SLP. See section “Sleep Mode” on page 20.
TABLE 13. SLEEP MODE SELECTION
CONTROL REGISTER BITS
SLP
OPERATION
0
Normal operation mode
1
Device enters Sleep mode
Current Sense Gain (CSG1, CSG0)
These bits set the gain of the current sense amplifier. These
are x10, x25, x80 and x160. For more detail, see section
“Current Monitor Function” on page 25.
TABLE 14. CURRENT SENSE GAIN CONTROL
CONTROL REGISTER BITS
CSG1
CSG0
OPERATION
0
0
Set current sense gain=x10
0
1
Set current sense gain=x25
1
0
Set current sense gain=x80
1
1
Set current sense gain=x160
Charge/Discharge Control (OVPC, UVPC)
The OVPC and UVPC bits allow control of cell charge and
discharge externally, via the SPI port. These bits control the
OVP/LMON and UVP/OCP pins, which in turn control the
external power FETs.
Using P-channel power FETs ensures that the FET is on
when the pin voltage is low (Vss), and off when the pin
voltage is high (Vcc).
OVP/LMON and UVP/OCP can be controlled by using the
WCNTR Instruction to set bits OVPC and UVPC in the
Control register (See page 17).
TABLE 15. UVP/OVP CONTROL
CONTROL REGISTER
BITS
OVPC
UVPC
OPERATION
1
x
Pin OVP = V_SS (FET ON)
0
x
Pin OVP = V_CC (FET OFF)
x
1
Pin UVP = V_SS (FET ON)
x
0
Pin UVP = V_CC (FET OFF)
It is possible to set/change the values of OVPC and UVPC
during a protection mode. A change in the state of the pins
OVP/LMON and UVP/OCP, however, will not take place until
the device has returned from the protection mode.
Cell Voltage Balance Control (CBC1–CBC3)
This function can be used to adjust individual battery cell
voltage during charging. Pins CB1–CB3 are used to control
external power switching devices. Cell voltage balancing is
achieved via the SPI port.
TABLE 16. CB1–CB3 CONTROL
Control Register Bits
CBC3 CBC2 CBC1
Operation
x
x
1
Set CB1 = V_CC (ON)
x
x
0
Set CB1 = V_SS (OFF)
x
1
x
Set CB2 = V_CC (ON)
x
0
x
Set CB2 = V_SS (OFF)
1
x
x
Set CB3 = V_CC (ON)
0
x
x
Set CB3 = V_SS (OFF)
x
x
x
Set CB4 = V_CC (ON)
x
x
x
Set CB4 = V_SS (OFF)
CB1–CB3 can be controlled by using the WCNTR Instruction
to set bits CBC1–CBC3 in the control register (Table 16).
Status Register
The status of the X3102 can be verified by using the
RDSTAT command to read the contents of the Status
Register (Table 17).
TABLE 17. STATUS REGISTER
76543
2
1
0
00000
CCES +
OVDS
UVDS
VRGS +
OCDS
17
FN8246.0
December 22, 2004