X3102 Datasheet, PDF (23/32 Pages) Intersil Corporation – 3 Cell Li-Ion Battery Protection and Monitor IC

X3102
Overcurrent Protection
In addition to monitoring the battery cell voltages, the X3102
continually monitors the voltage VCS₂₁ (VCS₂–VCS₁)
across the current sense resistor (R_SENSE). If VCS₂₁ > V_OC
for a time exceeding T_OC, then the device enters overcurrent
protection mode (Figure 7). In this mode, the X3102
automatically switches the discharge FET OFF (UVP/OCP =
Vcc) and hence prevent current from flowing through the
terminals P+ and P-.
X3102
Q2
OVP/LMON
P+
I_LMON
D1
V_RGO
Q10
R_OCR
(Load)
FET Control
Circuitry
T_OCR (ms) ≈ 10,000 x C_OC (µF)
TABLE 23. TYPICAL OVERCURRENT DELAY TIMES
Symbol
Description
T_OC
Overcurrent
detection delay
C_OC
0.001µF
Delay
10ms (Typ)
T_OCR Overcurrent
release time
0.001µF
10ms (Typ)
The value of V_OC can be selected from the values shown in
Table 6, by setting bits VOC1, VOC0 in the configuration
register using the WCFIG command.
Note: If the Charge FET is turned off, due to an overcharge
condition or by direct command from the microcontroller, the
cells are not in an undervoltage condition and the pack has a
load, then excessive current may flow through Q10 and
diode D1. To eliminate this effect, the gate of Q10 can be
turned off by the microcontroller.
VSS
VCS1
VCS2
P-
R_SENSE
FIGURE 13. OVERCURRENT PROTECTION
The 5VDC voltage regulator output (V_RGO) is always active
during an overcurrent protection mode.
Once the device enters overcurrent protection mode, the
X3102 begin a load monitor state. In the load monitor state, a
small current (I_LMON = 7.5µA typ.) is passed out of pin OVP/
LMON in order to determine the load resistance. The load
resistance is the impedance seen looking out of pin OVP/
LMON, between terminal P+ and pin VSS (See Figure 13.)
If the load resistance > R_OCR (I_LMON = 0µA) for a time
exceeding T_OCR, then the X3102 is released from
overcurrent protection mode. The discharge FET is then
automatically switched ON (UVP/OCP = Vss) by the X3102,
unless the status of UVP/OCP has been changed in control
register (by manipulating bit UVPC) during the overcurrent
protection mode.
T_OC/T_OCR are varied using a capacitor (C_OC) connected
between pin OCT and VSS. A list of typical delay times is
shown in Table 23. Note that the value C_OC should be larger
than 1nF.
The delay T_OC and T_OCR that results from a particular
capacitance C_OC can be approximated by the following
equations:
T_OC (ms) ≈ 10,000 x C_OC (µF)
23
FN8246.0
December 22, 2004