X3102 Datasheet, PDF (26/32 Pages) Intersil Corporation – 3 Cell Li-Ion Battery Protection and Monitor IC

X3102
Voltage Regulator
The X3102 is able to supply peripheral devices with a regulated
5VDC±0.5% output at pin RGO. The voltage regulator should
be configured externally as shown in Figure 16.
The non-inverting input of OP1 is fed with a high precision
5VDC supply. The voltage at the output of the voltage
regulator (V_RGO) is compared to this 5V reference via the
inverting input of OP1. The output of OP1 in turn drives the
regulator pnp transistor (Q1). The negative feedback at the
regulator output maintains the voltage at 5VDC ±0.5%
(including ripple) despite changes in load, and differences in
regulator transistors.
When power is applied to pin VCC of the X3102, V_RGO is
regulated to 5VDC±10% for a nominal time of T_OC+2ms.
During this time period, V_RGO is “tuned” to attain a final
value of 5VDC ±0.5% (Figure 8).
The maximum current that can flow from the voltage
regulator (I_LMT) is controlled by the current limiting resistor
(R_LMT) connected between RGP and VCC. When the voltage
across VCC and RGP reaches a nominal 2.5V (i.e. the
threshold voltage for the FET), Q2 switches ON, shorting VCC
to the base of Q1. Since the base voltage of Q1 is now
higher than the emitter voltage, Q1 switches OFF, and hence
the supply current goes to zero.
Typical values for R_LMT and I_LMT are shown in Table 27. In
order to protect the voltage regulator circuitry from damage
in case of a short-circuit, R_LMT ≥ 10Ω should always be
used.
TABLE 27. TYPICAL VALUES FOR R_LMT AND I_LMT
R_LMT
10Ω
VOLTAGE REGULATOR CURRENT LIMIT (I_LMT)
250mA ± 50% (Typical)
25Ω
100mA ± 50% (Typical)
50Ω
50mA ± 50% (Typical)
When choosing the value of R_LMT, the drive limitations of the
PNP transistor used should also be taken into consideration.
The transistor should have a gain of at least 100 to support
an output current of 250mA.
To Internal Voltage
Regulating Circuitry
X3102
Tuning
VCC
RGP
Q2
Un-Regulated
Voltage
Input
R_LMT
I_LMT
5VDC
Precision
Voltage
Reference
+
_
OP1
RGC
RGO
Q1
Regulated
5VDC Output
0.1 ^VRGO
µF
FIGURE 16. VOLTAGE REGULATOR OPERATION
4KBit EEPROM Memory
The X3102 contains a CMOS 4k-bit serial EEPROM,
internally organized as 512 x 8 bits. This memory is
accessible via the SPI port, and features the IDLock
function.
The 4kbit EEPROM array can be accessed by the SPI port at
any time, even during a protection mode, except during sleep
mode. After power is applied to VCC of the X3102, EEREAD
and EEWRITE Instructions can be executed only after times
t_PUR (power up to read time) and t_PUW (power up to write
time) respectively.
IDLock is a programmable locking mechanism which allows
the user to lock data in different portions of the EEPROM
memory space, ranging from as little as one page to as
much as 1/2 of the total array. This is useful for storing
information such as battery pack serial number,
manufacturing codes, battery cell chemistry data, or cell
characteristics.
EEPROM Write Enable Latch
The X3102 contains an EEPROM “Write Enable” latch. This
latch must be SET before a write to EEPROM operation is
initiated. The WREN instruction will set the latch and the
WRDI instruction will reset the latch (Figure 17). This latch is
automatically reset upon a power-up condition and after the
completion of a byte or page write cycle.
IDLock Memory
Intersil’s IDLock memory provides a flexible mechanism to
store and lock battery cell/pack information. There are seven
distinct IDLock memory areas within the array which vary in
size from one page to as much as half of the entire array.
26
FN8246.0
December 22, 2004