X3102 Datasheet, PDF (21/32 Pages) Intersil Corporation – 3 Cell Li-Ion Battery Protection and Monitor IC

X3102
UVP/OCP and OVP/LMON via bits UVPC and OVPC in the
control register is also prohibited.
The device returns from sleep mode when V_CC ≥ V_SLR. (e.g.
when the battery terminals are connected to a battery
charger). In this case, the X3102 restores the 5VDC
regulated output (section “Voltage Regulator” on page 26),
and communication via the SPI port resumes.
If the Cell Charge Enable function is enabled when V_CC
rises above V_SLR, the X3102 internally verifies that the
individual battery cell voltages (V_CELL) are larger than the
cell charge enable voltage (V_CE) before allowing the FETs to
be turned on. The value of V_CE is selected by using the
WCFIG command to set bits VCE1–VCE0 in the
configuration register.
Only if the condition “V_CELL > V_CE” is satisfied can
the state of charge and discharge FETs be changed via the
control register. Otherwise, if V_CELL < V_CE for any battery
cell then both the Charge FET and the discharge FET are OFF
(OVP/LMON = V_CC and UVP/OCP = V_CC). Thus both charge
and discharge of the battery cells via terminals P+ / P- is
prohibited (See Note).
NOTE: In this case, charging of the battery may resume ONLY if the
cell charge enable function is switched OFF by setting bit SWCEN=1
in the configuration register (See Above, “CONFIGURATION
REGISTER FUNCTIONALITY” on page 15).
The cell charging threshold function can be switched ON or
OFF by the user, by setting bit SWCEN in the configuration
register (Table 7) using the WCFIG command. In the case
that this cell charge enable function is switched OFF, then
V_CE is effectively set to 0V.
The X3102 cannot enter sleep mode (automatically or
manually, by setting the SLP bit) if V_CC ≥ V_SLR. This is to
ensure that the device does not go into a sleep mode while
the battery cells are at a high voltage (e.g. during cell
charging).
V_CC
VCELL
V_UV
0.7V
Cell Charge Prohibited if SWCEN=0
AND V_CELL < V_CE
T_UVR
V_SLR
V_UVR
V_CE
UVP/OCP
OVP/LMON
RGO
T_UV
Over-discharge Protection Mode
The Longer of TOV+200ms OR TUV+200ms
Sleep Mode
Notes 1, 2
Note 3
V_CC
V_SS
V_CC
V_SS
5V
Event
0
1
2
0V
3
4
5
NOTES:
1. If SWEN=0 and V_CELL < V_CE, then OVP/LMON stays high and charging is prohibited.
2. OVP/LMON stays high until the microcontroller writes a “1” to the OVPC bit in the control register. This sets the signal low, which turns on the charge FET. It cannot be turned
on prior to this time.
3. UVP/OCP stays high until the microcontroller writes a “1” to the UVPC bit in the control register. This sets the signal low, which turns on the discharge FET. The FET cannot
be turned on prior to this time.
FIGURE 12. OVER-DISCHARGE PROTECTION MODE-EVENT DIAGRAM
21
FN8246.0
December 22, 2004