X3102 Datasheet, PDF (27/32 Pages) Intersil Corporation – 3 Cell Li-Ion Battery Protection and Monitor IC

X3102
Prior to any attempt to perform an IDLock operation, the
WREN instruction must first be issued. This instruction sets
the “Write Enable” latch and allows the part to respond to an
IDLock sequence. The EEPROM memory may then be
IDLocked by writing the SET IDL instruction (Table 30 and
Figure 25), followed by the IDLock protection byte.
TABLE 28. IDLock PARTITION BYTE DEFINITION
IDLock PROTECTION
BYTES
EEPROM MEMORY ADDRESS
IDLocked
0000 0000
None
0000 0001
000h–07Fh
0000 0010
080h–0FFh
0000 0011
100h–17Fh
0000 0100
180h–1FFh
0000 0101
000h–0FFh
0000 0110
000h–00Fh
0000 0111
1F0h–1FFh
The IDLock protection byte contains the IDLock bits IDL2-
IDL0, which defines the particular partition to be locked
(Table 28). The rest of the bits [7:3] are unused and must be
written as zeroes. Bringing CS HIGH after the two byte
IDLock instruction initiates a nonvolatile write to the status
register. Writing more than one byte to the status register will
overwrite the previously written IDLock byte.
Once an IDLock instruction has been completed, that IDLock
setup is held in a nonvolatile IDLock Register (Table 29) until
the next IDLock instruction is issued. The sections of the
memory array that are IDLocked can be read but not written
until IDLock is removed or changed.
TABLE 29. IDLock REGISTER
7
6
5
4
3
2
1
0
0
0
0
0
0 IDL2 IDL1 IDL0
NOTE: Bits [7:3] specified to be “0’s”.
X3102 SPI Serial Communication
The X3102 is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families. This interface uses four
signals, CS, SCK, SI and SO. The signal CS when low,
enables communications with the device. The SI pin carries
the input signal and SO provides the output signal. SCK
clocks data in or out. The X3102 operates in SPI mode 0
which requires SCK to be normally low when not transferring
data. It also specifies that the rising edge of SCK clocks data
into the device, while the falling edge of SCK clocks data out.
This SPI port is used to set the various internal registers,
write to the EEPROM array, and select various device
functions.
The X3102 contains an 8-bit instruction register. It is
accessed by clocking data into the SI input. CS must be
LOW during the entire operation. Table 30 contains a list of
the instructions and their opcodes. All instructions,
addresses and data are transferred MSB first.
Data input is sampled on the first rising edge of SCK after
CS goes LOW. SCK is static, allowing the user to stop the
clock, and then start it again to resume operations where
left off.
TABLE 30. INSTRUCTION SET
INSTRUCTION
NAME
INSTRUCTION
FORMAT*
DESCRIPTION
WREN
0000 0110 Set the write enable latch (write enable operation) (Figure 17)
WRDI
0000 0100 Reset the write enable latch (write disable operation) (Figure 17)
EEWRITE
0000 0010 Write command followed by address/data (4kbit EEPROM) (Figure 18, Figure 19)
EEREAD STAT
0000 0101 Reads IDLock settings & status of EEPROM EEWRITE instruction (Figure 20)
EEREAD
0000 0011 Read operation followed by address (for 4kbit EEPROM) (Figure 21)
WCFIG
0000 1001
Write to configuration register followed by two bytes of data (Figure 10, Figure 22). Data stored in
SRAM only and will power-up to previous settings (Figure 9)
WCNTR
0000 1010 Write to control register, followed by two bytes of data (Figure 23)
RDSTAT
0000 1011 Read contents of status register (Figure 24)
SET IDL
0000 0001 Set EEPROM ID lock partition followed by partition byte (Figure 25)
*Instructions have the MSB in leftmost position and are transferred MSB first.
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FN8246.0
December 22, 2004