BD82HM55QMNT Datasheet, PDF (918/934 Pages) Intel Corporation – Intel® 5 Series Chipset and Intel® 3400 Series Chipset

Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
23.8.12 IDESBMDS1R—IDE Secondary Bus Master Device
Specific 1 Register (IDER—D22:F2)
Address Offset: 0Bh
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
Device Specific Data1 (DSD1)—R/W. This register implements the bus master
7:0 Device Specific 1 register of the secondary channel. This register is programmed by
the Host for device specific data if any.
23.8.13 IDESBMDTPR0—IDE Secondary Bus Master Descriptor
Table Pointer Byte 0 Register (IDER—D22:F2)
Address Offset: 0Ch
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
Descriptor Table Pointer Byte 0 (DTPB0)—R/W. This register implements the
7:0
Byte 0 (1 of 4 bytes) of the descriptor table Pointer (four I/O byte addresses) for bus
master operation of the secondary channel. This register is read/write by the HOST
interface.
23.8.14 IDESBMDTPR1—IDE Secondary Bus Master Descriptor
Table Pointer Byte 1 Register (IDER—D22:F2)
Address Offset: 0Dh
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
Descriptor Table Pointer Byte 1 (DTPB1)—R/W. This register implements the
7:0 Byte 1 (of four bytes) of the descriptor table Pointer (four I/O byte addresses) for bus
master operation of the secondary channel. This register is programmed by the Host.
918
Datasheet