BD82HM55QMNT Datasheet, PDF (32/934 Pages) Intel Corporation – Intel® 5 Series Chipset and Intel® 3400 Series Chipset

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PCH Interface Signals Block Diagram ......................................................................54
Example External RTC Circuit.................................................................................92
PCH High-Level Clock Diagram ............................................................................. 115
Generation of SERR# to Platform ......................................................................... 124
LPC Interface Diagram ........................................................................................ 133
PCH DMA Controller............................................................................................ 138
DMA Request Assertion through LDRQ# ................................................................ 141
TCO Legacy/Compatible Mode SMBus Configuration ................................................ 187
Advanced TCO Mode ........................................................................................... 188
Serial Post over GPIO Reference Circuit ................................................................. 190
Flow for Port Enable / Device Present Bits.............................................................. 198
Serial Data transmitted over the SGPIO Interface ................................................... 202
EHCI with USB 2.0 with Rate Matching Hub ........................................................... 218
PCH Intel^® Management Engine High-Level Block Diagram ...................................... 248
Flash Partition Boundary ..................................................................................... 252
Flash Descriptor Sections .................................................................................... 253
Analog Port Characteristics .................................................................................. 262
LVDS Signals and Swing Voltage .......................................................................... 264
LVDS Clock and Data Relationship ........................................................................ 264
Panel Power Sequencing ..................................................................................... 265
HDMI Overview.................................................................................................. 266
DP Overview...................................................................................................... 267
SDVO Conceptual Block Diagram .......................................................................... 269
PCH Ballout (top view—left side) (Desktop) ........................................................... 276
PCH Ballout (top view—right side) (Desktop) ......................................................... 277
PCH ballout (top View—Leff side) (Mobile Only) ...................................................... 287
PCH ballout (top View—right side) (Mobile Only)..................................................... 288
PCH ballout (top view—left side) (Mobile SFF Only) ................................................. 299
PCH ballout (top view—right side) (Mobile SFF Only) ............................................... 300
PCH Desktop Package Drawing............................................................................. 312
PCH B-Step Mobile Package Drawing..................................................................... 314
PCH Mobile SFF Package Drawing ......................................................................... 316
G3 w/RTC Loss to S4/S5 Timing Diagram .............................................................. 352
S5 to S0 Timing Diagram .................................................................................... 352
S3/M3 to S0 Timing Diagram ............................................................................... 353
S5/Moff - S5/M3 Timing Diagram ......................................................................... 353
S0 to S5 Timing Diagram .................................................................................... 354
DRAMPWRGD Timing Diagram ............................................................................. 354
Clock Cycle Time................................................................................................ 355
Transmitting Position (Data to Strobe) .................................................................. 355
Clock Timing...................................................................................................... 355
Setup and Hold Times......................................................................................... 356
Float Delay........................................................................................................ 356
Pulse Width ....................................................................................................... 356
Valid Delay from Rising Clock Edge ....................................................................... 356
Output Enable Delay........................................................................................... 357
USB Rise and Fall Times ...................................................................................... 357
USB Jitter ......................................................................................................... 357
USB EOP Width .................................................................................................. 358
SMBus Transaction ............................................................................................. 358
SMBus Timeout.................................................................................................. 358
SPI Timings ....................................................................................................... 359
Intel^® High Definition Audio Input and Output Timings ............................................ 359
Dual Channel Interface Timings............................................................................ 360
Dual Channel Interface Timings............................................................................ 360
LVDS Load and Transition Times .......................................................................... 360
Transmitting Position (Data to Strobe) .................................................................. 361
PCI Express Transmitter Eye................................................................................ 361
PCI Express Receiver Eye .................................................................................... 362
Measurement Points for Differential Waveforms...................................................... 363
PCH Test Load ................................................................................................... 364
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Datasheet