BD82HM55QMNT Datasheet, PDF (904/934 Pages) Intel Corporation – Intel® 5 Series Chipset and Intel® 3400 Series Chipset

Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
23.6.7
IDESCOR0—IDE Sector Count Out Register Device
0 Register (IDER—D22:F2)
Address Offset: 02h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
This register is read by the HOST interface if DEV = 0. ME-Firmware writes to this
register at the end of a command of the selected device.
When the host writes to this address, the IDE Sector Count In Register (IDESCIR), this
register is updated.
23.6.8
Bit
Description
7:0
IDE Sector Count Out Dev0 (ISCOD0)—R/W. Sector Count register for Master
Device (that is, Device 0).
IDESNOR0—IDE Sector Number Out Register
Device 0 Register (IDER—D22:F2)
Address Offset: 03h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
This register is read by the Host if DEV = 0. ME-Firmware writes to this register at the
end of a command of the selected device.
When the host writes to the IDE Sector Number In Register (IDESNIR), this register is
updated with that value.
Bit
Description
7:0
IDE Sector Number Out DEV 0 (IDESNO0)—R/W. Sector Number Out register for
Master device.
904
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