BD82HM55QMNT Datasheet, PDF (225/934 Pages) Intel Corporation – Intel® 5 Series Chipset and Intel® 3400 Series Chipset

Functional Description
Table 5-42. Enables for SMBus Slave Write and SMBus Host Events
Event
INTREN (Host
Control I/O
Register, Offset
02h, Bit 0)
SMB_SMI_EN (Host
Configuration
Register,
D31:F3:Offset 40h,
Bit1)
Event
Slave Write to Wake/
SMI# Command
X
Slave Write to
SMLINK_SLAVE_SMI
X
Command
Any combination of
0
Host Status Register
1
[4:1] asserted
1
Wake generated when
X
asleep.
Slave SMI# generated when
awake (SMBUS_SMI_STS).
Slave SMI# generated when
X
in the S0 state
(SMBUS_SMI_STS)
X
None
0
Interrupt generated
1
Host MI# enerated
Sg
Table 5-43. Enables for the Host Notify Command
HOST_NOTIFY_INTRE
N (Slave Control I/O
Register, Offset 11h,
bit 0)
SMB_SMI_EN (Host
Config Register,
D31:F3:Off40h, Bit 1)
HOST_NOTIFY_WKEN
(Slave Control I/O
Register, Offset 11h,
bit 1)
Result
0
X
0
None
X
X
1
Wake enerated
g
1
0
X
Interrupt generated
Slave SMI#
1
1
X
generated
(SMBUS_SMI_STS)
5.20.5 SMBALERT#
SMBALERT# is multiplexed with GPIO[11]. When enable and the signal is asserted, the
PCH can generate an interrupt, an SMI#, or a wake event from S1–S5.
5.20.6 SMBus CRC Generation and Checking
If the AAC bit is set in the Auxiliary Control register, the PCH automatically calculates
and drives CRC at the end of the transmitted packet for write cycles, and will check the
CRC for read cycles. It will not transmit the contents of the PEC register for CRC. The
PEC bit must not be set in the Host Control register if this bit is set, or unspecified
behavior will result.
If the read cycle results in a CRC error, the DEV_ERR bit and the CRCE bit in the
Auxiliary Status register at offset 0Ch will be set.
Datasheet
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