BD82HM55QMNT Datasheet, PDF (896/934 Pages) Intel Corporation – Intel® 5 Series Chipset and Intel® 3400 Series Chipset

Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
23.5.11 SCTLBA—Secondary Control Block base Address
Register (IDER—D22:F2)
Address Offset: 1C-1Fh
Default Value: 00000001h1
Attribute:
Size:
RO, R/W
32 bits
Bit
Description
31:16
15:2
1
0
Reserved
Base Address (BAR)—R/W. Base Address of the I/O space (4 consecutive I/O
locations).
Reserved
Resource Type Indicator (RTE)—RO. This bit indicates a request for I/O space.
23.5.12 LBAR—Legacy Bus Master Base Address Register
(IDER—D22:F2)
Address Offset: 20-23h
Default Value: 00000001h
Attribute:
Size:
RO, R/W
32 bits
Bit
Description
31:16
15:4
3:1
0
Reserved
Base Address (BA)—R/W. Base Address of the I/O space (16 consecutive I/O
locations).
Reserved
Resource Type Indicator (RTE)—RO. This bit indicates a request for I/O space.
23.5.13 SVID—Subsystem Vendor ID Register (IDER—D22:F2)
Address Offset: 2Ch–2Dh
Default Value: 0000h
Attribute:
Size:
R/WO
16 bits
Bit
15:0
Description
Subsystem Vendor ID (SSVID)—R/WO. Indicates the sub-system vendor identifier.
This field should be programmed by BIOS during boot-up. Once written, this register
becomes Read Only. This field can only be cleared by PLTRST#.
23.5.14 SID—Subsystem ID Register (IDER—D22:F2)
Address Offset: 2Eh–2Fh
Default Value: 0000h
Attribute:
Size:
R/WO
16 bits
Bit
15:0
Description
Subsystem ID (SSID)—R/WO. Indicates the sub-system identifier. This field should
be programmed by BIOS during boot-up. Once written, this register becomes Read
Only. This field can only be cleared by PLTRST#.
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Datasheet