BD82HM55QMNT Datasheet, PDF (917/934 Pages) Intel Corporation – Intel® 5 Series Chipset and Intel® 3400 Series Chipset

Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
23.8.9
IDESBMCR—IDE Secondary Bus Master Command
Register (IDER—D22:F2)
Address Offset: 08h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:4 Reserved
Read Write Command (RWC)—R/W. This bit sets the direction of bus master
3
transfer. When 0, Reads are performed from system memory; when 1, writes are
performed to System Memory. This bit should not be changed when the bus master
function is active.
2:1 Reserved
Start/Stop Bus Master (SSBM)—R/W. This bit gates the bus master operation of
IDE function when zero.
0
Writing 1 enables the bus master operation. Bus master operation can be halted by
writing a 0 to this bit. Operation cannot be stopped and resumed.
This bit is cleared after data transfer is complete as indicated by either the BMIA bit
or the INT bit of the Bus Master status register is set or both are set.
23.8.10 IDESBMDS0R—IDE Secondary Bus Master Device
Specific 0 Register (IDER—D22:F2)
Address Offset: 09h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
Device Specific Data0 (DSD0)—R/W. This register implements the bus master
7:0 Device Specific 1 register of the secondary channel. This register is programmed by
the Host.
23.8.11 IDESBMSR—IDE Secondary Bus Master Status
Register (IDER—D22:F2)
Address Offset: 0Ah
Default Value: 80h
Attribute:
Size:
R/W, RO
8 bits
Bit
Description
Simplex Only (SO)—R/W. This bit indicates whether both Bus Master Channels can
be operated at the same time or not.
7
0 = Both can be operated independently
1 = Only one can be operated at a time.
6
Drive 1 DMA Capable (D1DC)—R/W. This bit is read/write by the host.
5
Drive 0 DMA Capable (D0DC)—R/W. This bit is read/write by the host.
4:0 Reserved
Datasheet
917