BD82HM55QMNT Datasheet, PDF (746/934 Pages) Intel Corporation – Intel® 5 Series Chipset and Intel® 3400 Series Chipset

SMBus Controller Registers (D31:F3)
18.2 SMBus I/O and Memory Mapped I/O Registers
The SMBus registers (see Table 18-2) can be accessed through I/O BAR or Memory BAR
registers in PCI configuration space. The offsets are the same for both I/O and Memory
Mapped I/O registers.
Table 18-2. SMBus I/O and Memory Mapped I/O Register Address Map
SMB_BASE
+ Offset
Mnemonic
Register Name
Default
Type
00h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah–0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
14h
16h
17h
HST_STS
HST_CNT
HST_CMD
XMIT_SLVA
HST_D0
HST_D1
HOST_BLOCK_DB
PEC
RCV_SLVA
SLV_DATA
AUX_STS
AUX_CTL
SMLINK_PIN_CTL
Host Status
Host Control
Host Command
Transmit Slave Address
Host Data 0
Host Data 1
Host Block Data Byte
Packet Error Check
Receive Slave Address
Receive Slave Data
Auxiliary Status
Auxiliary Control
SMLink Pin Control (TCO
Compatible Mode)
SMBus_PIN_CTL SMBus Pin Control
SLV_STS
SLV_CMD
NOTIFY_DADDR
NOTIFY_DLOW
NOTIFY_DHIGH
Slave Status
Slave Command
Notify Device Address
Notify Data Low Byte
Notify Data High Byte
00h
00h
00h
00h
00h
00h
00h
00h
44h
0000h
00h
00h
See register
description
See register
description
00h
00h
00h
00h
00h
R/WC, RO
R/W, WO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
R/WC, RO
R/W
R/W, RO
R/W, RO
R/WC
R/W
RO
RO
RO
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