BD82HM55QMNT Datasheet, PDF (773/934 Pages) Intel Corporation – Intel® 5 Series Chipset and Intel® 3400 Series Chipset

PCI Express* Configuration Registers
19.1.27 DSTS—Device Status Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 4Ah–4Bh
Default Value: 0010h
Attribute:
Size:
R/WC, RO
16 bits
Bit
Description
15:6
5
4
3
2
1
0
Reserved
Transactions Pending (TDP)—RO. This bit has no meaning for the root port since
only one transaction may be pending to the PCH, so a read of this bit cannot occur until
it has already returned to 0.
AUX Power Detected (APD)—RO. The root port contains AUX power for wakeup.
Unsupported Request Detected (URD)—R/WC. Indicates an unsupported request
was detected.
Fatal Error Detected (FED)—R/WC. Indicates a fatal error was detected.
0 = Fatal has not occurred.
1 = A fatal error occurred from a data link protocol error, link training error, buffer
overflow, or malformed TLP.
Non-Fatal Error Detected (NFED)—R/WC. Indicates a non-fatal error was detected.
0 = Non-fatal has not occurred.
1 = A non-fatal error occurred from a poisoned TLP, unexpected completions,
unsupported requests, completer abort, or completer timeout.
Correctable Error Detected (CED)—R/WC. Indicates a correctable error was
detected.
0 = Correctable has not occurred.
1 = The port received an internal correctable error from receiver errors / framing
errors, TLP CRC error, DLLP CRC error, replay num rollover, replay timeout.
19.1.28 LCAP—Link Capabilities Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 4Ch–4Fh
Default Value: See bit description
Attribute:
Size:
R/WO, RO
32 bits
Bit
Description
Port Number (PN)—RO. Indicates the port number for the root port. This value is
different for each implemented port:
31:24
Function
D28:F0
D28:F1
D28:F2
D28:F3
D28:F4
D28:F5
D28:F6
D28:F7
Port #
1
2
3
4
5
6
7
8
Value of PN Field
01h
02h
03h
04h
05h
06h
07h
08h
Datasheet
773