BD82HM55QMNT Datasheet, PDF (235/934 Pages) Intel Corporation – Intel® 5 Series Chipset and Intel® 3400 Series Chipset

Functional Description
5.21.2.2
I²C Write Commands to the Intel^® ME
Table 5-49 lists the write commands supported by the Intel^® ME.
All bits in the write commands must be written to the PCH or the operation will be
aborted. For example, for 6-bytes write commands, all 48 bits must be written or the
operation will be aborted.
The command format follows the Block Write format of the SMBus specification.
Table 5-49. I²C Write Commands to the ME
Transaction
Slave
Addr
Data
Byte0
(Commd)
Data
Byte 1
(Byte
Count)
Data
Byte 2
Data
Byte 3
Data
Byte 4
Data
Byte 5
Data
Data
Byte 6 Byte 7
Write STS
Register (See
I²C
Note below)
41h
6h
STS
STS
STS
STS
STS
[47:40] [39:32] [31:24] [23:16] [15:8]
STS
[7:0]
Write
Lower Lower Upper Upper
Processor Core
I²C
42h
4h
Limit
Limit
Limit
Limit
Temp Limits
[15:8] [7:0] [15:8] [7:0]
Write Memory
Controller/
Graphics Temp
I²C
Limits
43h
Lower Upper
2h
Limit
Limit
[7:0]
[7:0]
Write PCH
Temp Limits
I²C
44h
Lower Upper
2h
Limit
Limit
[7:0]
[7:0]
Write DIMM
Temp Limits
I²C
45h
Lower Upper
2h
Limit
Limit
[7:0]
[7:0]
Write
Power Power
Processor Core
I²C
50h
2h
Clamp Clamp
Power Clamp
[15:8] [7:0]
NOTE: The Status Register (STS register) is only writable by an external controller and readable
by host SW. Whenever the controller writes to this register, an interrupt, if enabled by
BIOS/OS, is sent to the host. The controller must always write a full 48 bits to update this
register. Writes of anything other than 6 bytes result in indeterminate behavior. For bit
definition of this register, see Section 22.2.26 and Section 22.2.29.
5.21.2.3 Block Read Command
The external controller may read thermal information from the PCH using the SMBus
Block Read Command. Byte-read and Word-read SMBus commands are not supported.
Note that the reads use a different address than the writes.
The command format follows the Block Read format of the SMBus spec.
The PCH and external controller are set up by BIOS with the length of the read that is
supported by the platform. The device must always do reads of the lengths set up by
BIOS.
The PCH supports any one of the following lengths: 1, 2, 4, 5, 9, 10, 14 or 20 bytes.
The data always comes in the order described in Table 5-50, where 0 is the first byte
received in time on the SMBus.
Datasheet
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