BD82HM55QMNT Datasheet, PDF (447/934 Pages) Intel Corporation – Intel® 5 Series Chipset and Intel® 3400 Series Chipset

Gigabit LAN Configuration Registers
12.1.12 MBARC—Memory Base Address Register C
(Gigabit LAN—D25:F0)
Address Offset: 18h–1Bh
Default Value: 00000001h
Attribute:
Size:
R/W, RO
32 bits
Internal registers, and memories, can be accessed using I/O operations. There are two
4B registers in the I/O mapping window: Addr Reg and Data Reg. Software may only
access a DWord at a time.
Bit
31:5
4:1
0
Description
Base Address (BA)—R/W. Software programs this field with the base address of this
region.
I/O Size (IOSIZE)—RO. I/O space size is 32 Bytes.
Memory / I/O Space (MIOS)—RO. Set to 1 indicating an I/O Space BAR.
12.1.13 SVID—Subsystem Vendor ID Register
(Gigabit LAN—D25:F0)
Address Offset: 2Ch–2Dh
Default Value: See bit description
Attribute:
Size:
RO
16 bits
Bit
15:0
Description
Subsystem Vendor ID (SVID)—RO. This value may be loaded automatically from
the NVM Word 0Ch upon power up depending on the "Load Subsystem ID" bit field in
NVM word 0Ah. A value of 8086h is default for this field upon power up ifthe NVM does
not respond or is not programmed. All functions are initialized to the same value.
12.1.14 SID—Subsystem ID Register
(Gigabit LAN—D25:F0)
Address Offset: 2Eh–2Fh
Default Value: See bit description
Attribute:
Size:
RO
16 bits
Bit
15:0
Description
Subsystem ID (SID)—RO. This value may be loaded automatically from the NVM
Word 0Bh upon power up or reset depending on the “Load Subsystem ID” bit field in
NVM word 0Ah with a default value of 0000h. This value is loadable from NVM word
location 0Ah.
12.1.15 ERBA—Expansion ROM Base Address Register
(Gigabit LAN—D25:F0)
Address Offset: 30h–33h
Default Value: See bit description
Attribute:
Size:
RO
32 bits
Bit
32:0
Description
Expansion ROM Base Address (ERBA)—RO. This register is used to define the
address and size information for boot-time access to the optional FLASH memory. If no
Flash memory exists, this register reports 00000000h.
Datasheet
447