BD82HM55QMNT Datasheet, PDF (382/934 Pages) Intel Corporation – Intel® 5 Series Chipset and Intel® 3400 Series Chipset

Chipset Configuration Registers
10.1.12 BCR—Backbone Configuration Register
Offset Address: 0220–0223h
Default Value: 00000000h
Attribute:
Size:
R/W
32-bit
Bit
31:7
6
5:3
2:0
Description
Reserved
BCR Field 2—R/W. BIOS must set this bit.
Reserved
BCR Field 1—R/W. BIOS program this field to 101b
10.1.13 RPC—Root Port Configuration Register
Offset Address: 0224–0227h
Attribute:
Default Value: 0000000yh (y = 00xxb) Size:
R/W, RO
32-bit
Bit
31:12
11
10:8
7
Description
Reserved
GBE Over PCIe Root Port Enable (GBEPCIERPEN):
0 = GbE MAC/PHY communication is not enabled over PCI Express.
1 = The PCI Express port selected by the GBEPCIEPORTSEL register will be used for
GbE MAC/PHY over PCI Express communication
The default value for this register is set by the GBE_PCIE_EN soft strap.
NOTE: GbE and PCIE will use the output of this register and not the soft strap.
GBE Over PCIe Root Port Select (GBEPCIERPSEL):
If the GBEPCIERPEN is a ‘1’, then this register determines which port is used for GbE
MAC/PHY communication over PCI Express. This register is set by soft strap and is
writable to support separate PHY on motherboard and docking station.
111 = Port 8 (Lane 7)
110 = Port 7 (Lane 6)
101 = Port 6 (Lane 5)
100 = Port 5 (Lane 4)
101 = Port 4 (Lane 3)
010 = Port 3 (Lane 2)
001 = Port 2 (Lane 1)
000 = Port 1 (Lane 0)
The default value for this register is set by the GBE_PCIEPORTSEL[2:0] soft strap.
NOTE: GbE and PCIE will use the output of this register and not the soft strap.
High Priority Port Enable (HPE)—R/W.
0 = The high priority path is not enabled.
1 = The port selected by the HPP field in this register is enabled for high priority. It
will be arbitrated above all other VC0 (including integrated VC0) devices.
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Datasheet