BD82HM55QMNT Datasheet, PDF (695/934 Pages) Intel Corporation – Intel® 5 Series Chipset and Intel® 3400 Series Chipset

Intel^® High Definition Audio Controller Registers (D27:F0)
17.1.10 LT—Latency Timer Register
(Intel^® High Definition Audio Controller—D27:F0)
Address Offset: 0Dh
Default Value: 00h
Attribute:
Size:
RO
8 bits
Bit
Description
7:0 Latency Timer—RO. Hardwired to 00
17.1.11 HEADTYP—Header Type Register
(Intel^® High Definition Audio Controller—D27:F0)
Address Offset: 0Eh
Default Value: 00h
Attribute:
Size:
RO
8 bits
17.1.12
Bit
Description
7:0 Header Type—RO. Hardwired to 00.
HDBARL—Intel^® High Definition Audio Lower Base Address
Register (Intel^® High Definition Audio—D27:F0)
Address Offset: 10h–13h
Default Value: 00000004h
Attribute:
Size:
R/W, RO
32 bits
17.1.13
Bit
Description
Lower Base Address (LBA)—R/W. Base address for the Intel^® High Definition Audio
31:14 controller’s memory mapped configuration registers. 16 Kbytes are requested by
hardwiring bits 13:4 to 0s.
13:4 Reserved.
3 Prefetchable (PREF)—RO. Hardwired to 0 to indicate that this BAR is NOT prefetchable
2:1
Address Range (ADDRNG)—RO. Hardwired to 10b, indicating that this BAR can be
located anywhere in 64-bit address space.
0
Space Type (SPTYP)—RO. Hardwired to 0. Indicates this BAR is located in memory
space.
HDBARU—Intel^® High Definition Audio Upper Base
Address Register
(Intel^® High Definition Audio Controller—D27:F0)
Address Offset: 14h–17h
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
Bit
31:0
Description
Upper Base Address (UBA)—R/W. Upper 32 bits of the Base address for the Intel^®
High Definition Audio controller’s memory mapped configuration registers.
Datasheet
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