BD82HM55QMNT Datasheet, PDF (556/934 Pages) Intel Corporation – Intel® 5 Series Chipset and Intel® 3400 Series Chipset

LPC Interface Bridge Registers (D31:F0)
13.10.19 GP_RST_SEL3—GPIO Reset Select
Offset Address: GPIOBASE +68h
Default Value: 00000000h
Lockable:
Yes
Attribute:
Size:
Power Well:
R/W
32-bit
Core for 0:7, 16:23,
Resume for 8:15, 24:31
Bit
Description
31:12
11:8
Reserved
GP_RST_SEL[75:72]—R/W.
0 = Corresponding GPIO registers will be reset by host partition reset, global resets,
and straight-to-S5 events such as THRMTRIP# or Power Button Override.
1 = Corresponding GPIO registers will be reset by RSMRST# assertion only.
NOTE: For a list of causes of host partition and global resets, see Table 5-35.
7:0 Reserved
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