80333 Datasheet, PDF (7/75 Pages) Intel Corporation – I/O Processor

80333
1.0
Introduction
1.1
1.1.1
About This Document
This document is the Intel^® 80333 I/O Processor Datasheet. This document contains a functional
overview, package signal locations, targeted electrical specifications, and bus functional
waveforms. Detailed functional descriptions other than parametric performance are published in
the Intel^® 80333 I/O Processor Developer’s Manual.
Intel Corporation assumes no responsibility for any errors which may appear in this document nor
does it make a commitment to update the information contained herein.
Intel retains the right to make changes to these specifications at any time, without notice. In
particular, descriptions of features, timings, packaging, and pin-outs does not imply a commitment
to implement them. In fact, this specification does not imply a commitment by Intel to design,
manufacture, or sell the product described herein.
Terminology
To aid the discussion of the Intel^® 80333 I/O processor (80333) architecture, the following
terminology is used:
Core processor
Local processor
Intel XScale^® core within the 80333
Intel XScale^® core within the 80333
Host processor
Processor located upstream from the 80333
Local bus
Local memory
80333 Internal Bus
Memory subsystem on the Intel XScale^® core DDR SDRAM or Peripheral Bus
Interface busses
Inbound
At or toward the Internal Bus of the 80333 from the PCI interface of the ATU
Outbound
At or toward the PCI interface of the 80333 ATU from the Internal Bus
Downstream
At or toward a PCI Express* port directed away from the root complex (to a bus
with a higher number)
Upstream
At or toward a PCI Express* port directed to the PCI Express* root complex (to
a bus with a lower number).
QWORD
64-bit data quantity (8 bytes).
DWORD
32-bit data quantity (4 bytes).
word
16-bit data quantity (2 bytes).
Datasheet
Intel^® 80333 I/O Processor Datasheet
Order Number: 305433, Revision: 002
May 2005
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