80333 Datasheet, PDF (60/75 Pages) Intel Corporation – I/O Processor

80333
Table 27. PCI Express* Clock Timings
Symbol
Parameter
Minimum
Nominal
Maximum
Units Notes
T_F2
PCI Express* clock
frequency
-300ppm
100
+300 ppm
MHz 1
T_C2
PCI Express* clock cycle
time
10
10.2
ns
2
T_CCJ Cycle to Cycle Jitter
Clock duty cycle
45
200
ps
55
%
T_rise
REFCLK rise time across
600mV
300
600
ps
3
T_fall
REFCLK fall time across
600mV
300
600
ps
3
Rise-Fall matching
20
%
3,4
Cross point at 1V
0.51
0.76
V
Rising edge ringback
0.85
V
Falling edge ringback
0.35
V
Notes:
1.
Spread spectrum clocking is allowed with the following three requirements;
a. All device timings must be met including jitter, skew, min./max. clock period. Output rise/fall timing MUST meet
the existing non-spread spectrum specifications.
b. All non-spread Host and PCI functionality must be maintained in the spread-spectrum mode (includes all power
management functions).
c. The minimum clock period cannot be violated. The preferred method is to adjust the spread technique to allow
for modulation above the nominal frequency. This technique is often called “down-spreading”.
2.
Measured at crossing point.
3.
Measured from V_OL = 0.2 V to V_OH = 0.8 V.
4.
Determined as a fraction of 2 × (Trise - Tfall)/(Trise + Tfall).
May 2005
60
Intel^® 80333 I/O Processor Datasheet
Order Number: 305433, Revision: 002
Datasheet