80333 Datasheet, PDF (29/75 Pages) Intel Corporation – I/O Processor

80333
Table 14.
Reset Strap Signals (Sheet 1 of 2)
Name
RETRY
CORE_RST#
P_BOOT16#
MEM_TYPE
A_PCIX133EN
B_PCIX133EN
Count
1
1
1
1
1
1
Type
C
C
C
C
C
C
Description
Configuration Retry Mode: RETRY is latched on the rising
(asserting) edge of PWRGD and determines when the PCI
interface of the ATU will disable PCI configuration cycles by
signaling a retry until the configuration cycle retry bit is cleared in
the PCI configuration and status register.
0 = Configuration Cycles enabled (Requires pull down resistor.)
1 = Configuration Retry enabled in the ATU (Default mode)
Note: Muxed onto signal AD[6], see Table 17, “Pin Multiplexing
for Functional Modes” on page 36.
Core Reset Mode is latched on the rising (asserting) edge of
PWRGD and determines when the Intel XScale^® core is held in
reset until the processor reset bit is cleared in PCI configuration
and status register.
0 = Hold in reset. (Requires pull-down resistor.)
1 = Do not hold in reset. (Default mode)
Note: Muxed onto signal AD[5], see Table 17, “Pin Multiplexing
for Functional Modes” on page 36.
Bus Width is latched on the rising (asserting) edge of PWRGD, it
sets the default bus width for the PBI Memory Boot window.
0 = 16 bits wide (Requires a pull-down resistor.)
1 = 8 bits wide (Default mode)
Note: Muxed onto signal AD[4], see Table 17, “Pin Multiplexing
for Functional Modes” on page 36.
Memory Type: MEM_TYPE is latched on the rising (asserting)
edge of PWRGD and it defines the speed of the DDR SDRAM
interface.
0 = DDR-II SDRAM at 400 MHz (Required pull-down resistor.)
1 = DDR SDRAM at 333 MHz (Default mode)
Note: Muxed onto signal AD[2], see Table 17, “Pin Multiplexing
for Functional Modes” on page 36.
PCI Bus Segment ‘A’ 133 MHz Enable: A_PCIX133EN is latched
on the rising (asserting) edge of PWRGD and it determines the
maximum PCI-X mode operating frequency.
0 = 100 MHz enabled (Requires pull down resistor).
1 = 133 MHz enabled (Default mode).
Note: Muxed onto signal AD[3], see Table 17, “Pin Multiplexing
for Functional Modes” on page 36.
PCI Bus Segment ‘B’ 133 MHz Enable: B_PCIX133EN latched
on rising (asserting) edge of PWRGD and determines maximum
PCI-X mode operating frequency.
0 = 100 MHz enabled (Requires pull down resistor.)
1 = 133 MHz enabled (Default mode)
Note: Muxed onto signal AD[10], see Table 17, “Pin Multiplexing
for Functional Modes” on page 36.
Datasheet
Intel^® 80333 I/O Processor Datasheet
Order Number: 305433, Revision: 002
May 2005
29